Markus Schwiegershausen

According to our database, Markus Schwiegershausen authored at least 10 papers between 1991 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1997

Ein Verfahren zur Optimierung heterogener Multiprozessorsysteme mittels linearer Programmierung.

Markus Schwiegershausen

PhD thesis, 1997

Implementation of pipelined multipliers on Xilinx FPGAs.

Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms.

Carsten Reuter, Markus Schwiegershausen, Peter Pirsch

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

A CAD tool for the optimization of video signal processor architectures.

Holger Kropp, Markus Schwiegershausen, Peter Pirsch

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

A system level HW/SW partitioning and optimization tool.

Markus Schwiegershausen, Holger Kropp, Peter Pirsch

Proceedings of the conference on European design automation, 1996

1995

The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.

Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner

J. VLSI Signal Process., 1995

A system level design methodology for the optimization of heterogeneous multiprocessors.

Markus Schwiegershausen, Peter Pirsch

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.

Markus Schwiegershausen, Peter Pirsch

Proceedings of the Proceedings EURO-DAC'95, 1995

1991

Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays.

Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch

Proceedings of the VLSI 91, 1991

Synthesis of intermediate memories for the data supply to processor arrays.

Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch

Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991