Peter Pirsch
Affiliations:- University of Hanover, Germany
According to our database1,
Peter Pirsch
authored at least 116 papers
between 1981 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1997, "For contributions to the architectural conception and VLSI implementation of digital video coding schemes.".
Timeline
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Bibliography
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2017
High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
2016
An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems.
Proceedings of the 2016 IEEE International Symposium on Signal Processing and Information Technology, 2016
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose.
Int. J. Parallel Program., 2013
2011
Using SDRAMs for two-dimensional accesses of long 2<sup>n</sup> × 2<sup>m</sup>-point FFTs and transposing.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the IEEE International Conference on Computer Vision Workshops, 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
2010
J. Signal Process. Syst., 2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the Architecture of Computing Systems, 2009
2008
Proceedings of the Embedded Computer Systems: Architectures, 2008
A parallel hardware architecture for connected component labeling based on fast label merging.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing.
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler.
Proceedings of the Architecture of Computing Systems, 2007
2006
Proceedings of the IEEE 8th Workshop on Multimedia Signal Processing, 2006
2005
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications.
J. VLSI Signal Process., 2005
J. VLSI Signal Process., 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
2004
SIGARCH Comput. Archit. News, 2004
SIGARCH Comput. Archit. News, 2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the 2004 IEEE International Geoscience and Remote Sensing Symposium, 2004
2003
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 IEEE International Geoscience and Remote Sensing Symposium, 2003
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003
Proceedings of the 2003 International Conference on Image Processing, 2003
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
Proceedings of the 2003 Design, 2003
2002
J. VLSI Signal Process., 2002
IEEE Trans. Circuits Syst. Video Technol., 2002
Highly efficient simulation environment for HDTV video decoder in VLSI design.
Proceedings of the Visual Communications and Image Processing 2002, 2002
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2002
A platform-independent methodology for performance estimation of streaming media applications.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications.
Proceedings of the IEEE International Conference on Acoustics, 2002
2001
J. VLSI Signal Process., 2001
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
IEEE J. Solid State Circuits, 2000
Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes).
Informationstechnik Tech. Inform., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
1999
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications.
J. VLSI Signal Process., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999
Proceedings of the Parallel Computation, 1999
1998
J. VLSI Signal Process., 1998
IEEE Trans. Circuits Syst. Video Technol., 1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the Field-Programmable Logic and Applications, 1998
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing.
Proceedings of the Computer Graphics International Conference, 1998
Architectures for digital signal processing.
Wiley, ISBN: 978-0-471-97145-0, 1998
1997
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.
J. VLSI Signal Process., 1997
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
1996
Design of a development system for multimedia applications based on a single chip multiprocessor array.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the conference on European design automation, 1996
Architekturen der digitalen Signalverarbeitung.
Informationstechnik, Teubner, ISBN: 978-3-519-06157-1, 1996
1995
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
J. VLSI Signal Process., 1995
Architecture and C++-programming environment of a highly parallel image signal processor.
Microprocess. Microprogramming, 1995
A system level design methodology for the optimization of heterogeneous multiprocessors.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
J. VLSI Signal Process., 1993
A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications.
J. VLSI Signal Process., 1993
Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite Broadcasting.
Eur. Trans. Telecommun., 1993
Single board image processing unit for vehicle guidance.
Proceedings of the VLSI 93, 1993
A Hierarchical Multiprocessor Achitecture for Video Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Compact hardware realization for Hough based extraction of line segments in image sequences for vehicle guidance.
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
IEEE Trans. Circuits Syst. Video Technol., 1992
1991
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays.
Proceedings of the VLSI 91, 1991
Synthesis of intermediate memories for the data supply to processor arrays.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991
1990
Proceedings of the Visual Communications and Image Processing '90: Fifth in a Series, 1990
1989
Proceedings of the IEEE International Conference on Acoustics, 1989
1985
1984
Circuit Technique for VLSI Design of a Video Codec.
Proceedings of the IEEE International Conference on Communications: Links for the Future, 1984
1983
Comput. Graph., 1983
1982
1981
IEEE Trans. Commun., 1981