Luiz Cláudio Villar dos Santos

Orcid: 0000-0002-9384-8347

According to our database1, Luiz Cláudio Villar dos Santos authored at least 42 papers between 1996 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2020
Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Incremental Layer Assignment Driven by an External Signoff Timing Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
Clock-Tree-Aware Incremental Timing-Driven Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Cache sizing for low-energy Elliptic Curve Cryptography.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Evaluating the impact of circuit legalization on incremental optimization techniques.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2013
Pre-silicon verification of multiprocessor SoCs: The case for on-the-fly coherence/consistency checking.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

On-the-fly verification of memory consistency with concurrent relaxed scoreboards.
Proceedings of the Design, Automation and Test in Europe, 2013

Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A template for the construction of efficient checkers with full verification guarantees.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Efficient verification of out-of-order behaviors with relaxed scoreboards.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

On ESL verification of memory consistency for system-on-chip multiprocessing.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Cache-tuning-aware scratchpad allocation from binaries.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Fast estimation of memory consumption for energy-efficient compilers.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Automatic generation of memory consistency tests for chip multiprocessing.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An early real-time checker for retargetable compile-time analysis.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Mapping Data and Code into Scratchpads from Relocatable Binaries.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A novel verification technique to uncover out-of-order DUV behaviors.
Proceedings of the 46th Design Automation Conference, 2009

2008
An open-source binary utility generator.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems.
Proceedings of the Embedded Computer Systems: Architectures, 2007

An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code.
Proceedings of the Embedded Computer Systems: Architectures, 2007

An Object-Oriented Framework for Improving Software Reuse on Automated Testing of Mobile Phones.
Proceedings of the Testing of Software and Communicating Systems, 2007

On the Limitations of Power Macromodeling Techniques.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Automatic Retargeting of Binary Utilities for Embedded Code Generation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A multi-model power estimation engine for accuracy optimization.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support.
Proceedings of the Embedded Computer Systems: Architectures, 2005

2003
Global scheduling and register allocation based on predicated execution.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
A code-motion pruning technique for global scheduling.
ACM Trans. Design Autom. Electr. Syst., 2000

1999
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation.
Proceedings of the 1999 Design, 1999

A Reordering Technique for Efficient Code Motion.
Proceedings of the 36th Conference on Design Automation, 1999

1996
A Constructive Method for Exploiting Code Motion.
Proceedings of the 9th International Symposium on System Synthesis, 1996


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