Masahiro Kainaga

According to our database, Masahiro Kainaga authored at least 3 papers between 1994 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.

Toru Shimizu, Masami Nakajima, Masahiro Kainaga

IEICE Trans. Electron., 2006

1995

Optimal Tile Size Adjustment in Compiling General DOACROSS Loop Nests.

Hiroshi Ohta, Yasuhiko Saito, Masahiro Kainaga, Hiroyuki Ono

Proceedings of the 9th international conference on Supercomputing, 1995

1994

A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems.

Tetsuhiko Okada, Susumu Narita, Osamu Nishii, Noriharu Hiratsuka, Nobuyuki Hayashi, Mitsuo Asai, Shinji Fujiwara, Mikiko Satoh, Junichi Nishimoto, Hirokazu Aoki, Kunio Uchiyama, Shigeru Matsuo, Hidehito Takewa, Kouji Yamada, Masahiro Kainaga, Norio Nakagawa, Masanobu Yamagami, Hiroshi Takeda, Tsuneo Funabashi

Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994