Osamu Nishii

According to our database1, Osamu Nishii authored at least 14 papers between 1994 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Low Power Platform for Embedded Processor LSIs.
IEICE Transactions, 2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Transactions, 2011

2010

2009
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Development of processor cores for digital consumer appliances.
Systems and Computers in Japan, 2006

SH-X: An embedded processor core for consumer appliances.
J. Embedded Computing, 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Transactions, 2006

2005
SH-X: an embedded processor core for consumer appliances.
SIGARCH Computer Architecture News, 2005

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Transactions, 2005

Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

1998
SH4 RISC multimedia microprocessor.
IEEE Micro, 1998

1994
A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994


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