Kunio Uchiyama

According to our database, Kunio Uchiyama authored at least 21 papers between 1993 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Edge Artificial Intelligence Chips for the Cyberphysical Systems Era.

Hiroshi Fuketa, Kunio Uchiyama

Computer, 2021

2019

Better Actions for Society 5.0: Using AI for Evidence-Based Policy Making That Keeps Humans in the Loop.

Yoshihiro Shiroishi, Kunio Uchiyama, Norihiro Suzuki

Computer, 2019

2018

Society 5.0: For Human Security and Well-Being.

Yoshihiro Shiroishi, Kunio Uchiyama, Norihiro Suzuki

Computer, 2018

2012

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation.

Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama

IEICE Trans. Electron., 2012

2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Foreword.

Kunio Uchiyama

IEICE Trans. Electron., 2009

2008

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.

Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEEE J. Solid State Circuits, 2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Software-cooperative power-efficient heterogeneous multi-core for media processing.

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Power-Efficient Heterogeneous Multicore Technology for Digital Convergence.

Kunio Uchiyama

Proceedings of the Advances in Computer Systems Architecture, 2007

2005

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.

Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai

Syst. Comput. Jpn., 2005

Guest Editors' Introduction: Energy-Efficient Design.

Kunio Uchiyama, Pradip Bose

IEEE Micro, 2005

2000

SH-5: The 64-Bit SuperH Architecture.

Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama

IEEE Micro, 2000

1999

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode.

Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama

IEEE J. Solid State Circuits, 1999

1998

SH4 RISC multimedia microprocessor.

Fumio Arakawa, Osamu Nishii, Kunio Uchiyama, Norio Nakagawa

IEEE Micro, 1998

Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.

Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura

Proceedings of the 35th Conference on Design Automation, 1998

1997

Functional verification of the superscalar SH-4 microprocessor.

Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama

Proceedings of the Proceedings IEEE COMPCON 97, 1997

1994

A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems.

Tetsuhiko Okada, Susumu Narita, Osamu Nishii, Noriharu Hiratsuka, Nobuyuki Hayashi, Mitsuo Asai, Shinji Fujiwara, Mikiko Satoh, Junichi Nishimoto, Hirokazu Aoki, Kunio Uchiyama, Shigeru Matsuo, Hidehito Takewa, Kouji Yamada, Masahiro Kainaga, Norio Nakagawa, Masanobu Yamagami, Hiroshi Takeda, Tsuneo Funabashi

Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994

1993

The Gmicro/500 superscalar microprocessor with branch buffers.

Kunio Uchiyama, Fumio Arakawa, Susumu Narita, Hirokazu Aoki, Ikuya Kawasaki, Shigezumi Matsui, Mitsuyoshi Yamamoto, Norio Nakagawa, Ikuo Kudo

IEEE Micro, 1993

Design Methodology for GMICRO^TM/500 TRON Microprocessor.

Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993