Masahisa Tamura

According to our database, Masahisa Tamura authored at least 5 papers between 1999 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving -96.4-dBm Sensitivity and -27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets.

Masahisa Tamura, Hideyuki Takano, Hironori Nakahara, Hiroaki Fujita, Naoya Arisaka, Satoru Shinke, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Fumitaka Kondo, Ken Yamamoto, Tomohiro Matsumoto, Yasushi Katayama

IEEE J. Solid State Circuits, 2020

30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI.

Masahisa Tamura, Hideyuki Takano, Satoru Shinke, Hiroaki Fujita, Hironori Nakahara, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Yasushi Katayama

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2014

Distributed object storage toward storage and usage of packet data in a high-speed network.

Masahisa Tamura, Ken Iizawa, Munenori Maeda, Jun Kato, Tatsuo Kumano, Yuji Nomura, Toshihiro Ozawa

Proceedings of the 16th Asia-Pacific Network Operations and Management Symposium, 2014

2012

A 1V 357Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90nm CMOS.

Masahisa Tamura, Fumitaka Kondo, Katsumi Watanabe, Yasunori Aoki, Yusuke Shinohe, Koki Uchino, Yuhei Hashimoto, Fumihiro Nishiyama, Hiroaki Miyachi, Ikuho Nagase, Itaru Uezono, Rie Hisamura, Itaru Maekawa

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

1999

Dynamic Load Balancing for Parallel Association Rule Mining on Heterogenous PC Cluster Systems.

Masahisa Tamura, Masaru Kitsuregawa

Proceedings of the VLDB'99, 1999