Maurice Keller

According to our database, Maurice Keller authored at least 11 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Network-on-Chip interconnect for pairing-based cryptographic IP cores.

Tom English, Emanuel M. Popovici, Maurice Keller, William P. Marnane

J. Syst. Archit., 2011

2009

Hardware Implementation of Pairings.

Maurice Keller, Robert Ronan, Andrew Byrne, Colin C. Murphy, William P. Marnane

Proceedings of the Identity-Based Cryptography, 2009

Elliptic Curve Cryptography on FPGA for Low-Power Applications.

Maurice Keller, Andrew Byrne, William P. Marnane

ACM Trans. Reconfigurable Technol. Syst., 2009

Low Energy ASIC Elliptic Curve Processor.

Maurice Keller, William P. Marnane

J. Low Power Electron., 2009

A low-power pairing-based cryptographic accelerator for embedded security applications.

Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

Energy Efficient Elliptic Curve Processor.

Maurice Keller, William P. Marnane

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Hardware architectures for the Tate pairing over GF(2^m).

Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy

Comput. Electr. Eng., 2007

Low Power Elliptic Curve Cryptography.

Maurice Keller, William P. Marnane

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

A GF(2^4m) Inverter and its Application in a Reconfigurable Tate Pairing Processor.

Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

FPGA Implementation of a <i>GF</i>(2^<i>m</i>) Tate Pairing Architecture.

Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

FPGA Implementation of a GF(2^4M) Multiplier for use in Pairing Based Cryptosystems.

Maurice Keller, Tim Kerins, William P. Marnane

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005