Tim Kerins

According to our database1, Tim Kerins authored at least 19 papers between 2002 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve.
J. Syst. Archit., 2007

Versatile hardware architectures for GF(p<sup>m</sup>) arithmetic in public key cryptography.
Integr., 2007

A flexible processor for the characteristic 3 η<sub>T</sub> pairing.
Int. J. High Perform. Syst. Archit., 2007

Public-Key Cryptography for RFID-Tags.
Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

2006
Hardware Implementation of the η<sup>T</sup> Pairing in Characteristic 3.
IACR Cryptol. ePrint Arch., 2006

An Elliptic Curve Processor Suitable For RFID-Tags.
IACR Cryptol. ePrint Arch., 2006

An Embedded Processor for a Pairing-Based Cryptosystem.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Security in Next Generation Consumer Electronic Devices.
Proceedings of the ISSE 2006, 2006

FPGA acceleration of the tate pairing in characteristic 2.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

FPGA Implementation of a <i>GF</i>(2<sup><i>m</i></sup>) Tate Pairing Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A Dedicated Processor for the eta Pairing.
IACR Cryptol. ePrint Arch., 2005

Efficient hardware for the Tate pairing calculation in characteristic three.
IACR Cryptol. ePrint Arch., 2005

FPGA Implementation of a GF(2<sup>4M</sup>) Multiplier for use in Pairing Based Cryptosystems.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
An FPGA implementation of a GF(p) ALU for encryption processors.
Microprocess. Microsystems, 2004

Single-chip FPGA implementation of a cryptographic co-processor.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Fast Modular Division for Application in ECC on Reconfigurable Logic.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2).
Proceedings of the Field-Programmable Logic and Applications, 2002


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