Medien Zeghid

Orcid: 0000-0001-8217-3455

According to our database1, Medien Zeghid authored at least 29 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Performance Enhancement of FSO Communication System Under Rainy Weather Environment Using a Novel Encryption Technique.
IEEE Access, 2024

2023
Speed/Area-Efficient ECC Processor Implementation Over GF(2<sup>m</sup>) on FPGA via Novel Algorithm-Architecture Co-Design.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Performance of Cipher Image Transmission in Free Space Optics Under Foggy Weather.
IEEE Access, 2023

2022
Fast Constant-Time Modular Inversion over Fp Resistant to Simple Power Analysis Attacks for IoT Applications.
Sensors, 2022

Optimized Continuous Wavelet Transform Algorithm Architecture and Implementation on FPGA for Motion Artifact Rejection in Radar-Based Vital Signs Monitoring.
IEEE Access, 2022

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor.
IEEE Access, 2022

Tools for Fast Metric Data Search in Structural Methods for Image Classification.
IEEE Access, 2022

2021
An efficient 2D encoding/decoding technique for optical communication system based on permutation vectors theory.
Multim. Syst., 2021

Modified Optical Burst Switching (OBS) Based Edge Node Architecture Using Real-Time Scheduling Techniques.
IEEE Access, 2021

Adaptive Transceiver Architecture With QoS Provision for OCDMA Network Based on Logic Gates.
IEEE Access, 2021

2020
An improved co-designed AES-ECC cryptosystem for secure data transmission.
Int. J. Inf. Comput. Secur., 2020

Two-Dimensional Permutation Vectors' (PV) Code for Optical Code Division Multiple Access Systems.
Entropy, 2020

2019
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA.
Microprocess. Microsystems, 2018

2017
High-Level Implementation of a Chaotic and AES Based Crypto-System.
J. Circuits Syst. Comput., 2017

Lightweight Encryption Algorithm Based on Modified XTEA for Low-Resource Embedded Devices.
Proceedings of the 21st International Database Engineering & Applications Symposium, 2017

Design and SystemC Implementation of Chaos-Based Enhancements for the Advanced Encryption Standard.
Proceedings of the 27th International Conference on Computer Theory and Applications, 2017

2016
Fast hardware implementation of ECDSA signature scheme.
Proceedings of the International Symposium on Signal, Image, Video and Communications, 2016

Efficient software implementation of RNS-montgomery modular multiplication for embedded system.
Proceedings of the International Image Processing, Applications and Systems, 2016

Efficient software implementation of the final exponentiation for pairing.
Proceedings of the International Image Processing, Applications and Systems, 2016

Performance evaluation and design considerations of lightweight block cipher for low-cost embedded devices.
Proceedings of the 13th IEEE/ACS International Conference of Computer Systems and Applications, 2016

A Selective Encryption Scheme with Multiple Security Levels for the H.264/AVC Video Coding Standard.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

Efficient Hybrid Encryption System Based on Block Cipher and Chaos Generator.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

2015
Area-Efficient Hardware Implementation of the Optimal Ate Pairing over BN curves.
IACR Cryptol. ePrint Arch., 2015

Proposed efficient arithmetic operations architectures for Hyperelliptic Curves Cryptosystems (HECC).
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

A new approach for encryption system based on block cipher algorithms and logistic function.
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2010
Design and Hardware Implementation of QoSS - AES Processor for Multimedia applications.
Trans. Data Priv., 2010

2009
Design of Reconfigurable Image Encryption Processor Using 2-D Cellular Automata Generator.
Int. J. Comput. Sci. Appl., 2009

2007
A Reconfigurable Implementation of the New Secure Hash Algorithm.
Proceedings of the The Second International Conference on Availability, 2007


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