Jiafeng Xie
Orcid: 0009-0002-3052-4019
According to our database1,
Jiafeng Xie
authored at least 67 papers
between 2010 and 2024.
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Bibliography
2024
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
2023
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography.
ACM Trans. Reconfigurable Technol. Syst., September, 2023
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
IACR Cryptol. ePrint Arch., 2023
VMA: Divide-and-Conquer Vectorized Map Annotation System for Large-Scale Driving Scene.
CoRR, 2023
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication.
IEEE Comput. Archit. Lett., 2023
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
PasCore: A Chinese Overlapping Relation Extraction Model Based on Global Pointer Annotation Strategy.
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC.
Proceedings of the International Conference on Field Programmable Technology, 2023
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
2022
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Emerg. Top. Comput., 2022
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU.
IACR Cryptol. ePrint Arch., 2022
J. Electron. Test., 2022
Certificateless signature schemes in Industrial Internet of Things: A comparative survey.
Comput. Commun., 2022
IEEE Comput. Archit. Lett., 2022
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor.
IEEE Access, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework.
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022
2021
Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision.
Proceedings of the IJCKG'21: The 10th International Joint Conference on Knowledge Graphs, Virtual Event, Thailand, December 6, 2021
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets.
Proceedings of the Knowledge Graph and Semantic Computing: Knowledge Graph Empowers New Infrastructure Construction, 2021
2020
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2<sup>m</sup>) based on Bivariate Polynomial Basis Representation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 27th ACM International Conference on Multimedia, 2019
Low-Complexity Systolic Multiplier for GF(2<sup>m</sup>) using Toeplitz Matrix-Vector Product Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2<sup>m</sup>) based on MSPB.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
2018
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2<sup>m</sup>) Based on Trinomials.
IEEE Trans. Multi Scale Comput. Syst., 2018
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2<sup>m</sup>).
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Reliable Inversion in GF(2<sup>8</sup>) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Novel Hybrid-Size Digit-Serial Systolic Multiplier over <i>GF</i>(2<sup><i>m</i></sup>).
Symmetry, 2018
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field.
IEEE Access, 2018
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the British Machine Vision Conference 2018, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2<sup>m</sup>) Based on NIST Polynomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
2015
High-Throughput Digit-Level Systolic Multiplier Over GF(2<sup>m</sup>) Based on Irreducible Trinomials.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Low-Latency High-Throughput Systolic Multipliers Over GF(2<sup>m</sup>) for NIST Recommended Pentanomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Computers, 2013
2012
Low-latency area-delay-efficient systolic multiplier over GF(2<sup>m</sup>) for a wider class of trinomials using parallel register sharing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter.
J. Comput., 2011
2010
FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures.
Microelectron. J., 2010