Chiou-Yng Lee
Orcid: 0000-0002-5344-7434
According to our database1,
Chiou-Yng Lee
authored at least 100 papers
between 2001 and 2022.
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Bibliography
2022
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor.
IEEE Access, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2<sup>m</sup>) based on Bivariate Polynomial Basis Representation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Low-Complexity Systolic Multiplier for GF(2<sup>m</sup>) using Toeplitz Matrix-Vector Product Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2<sup>m</sup>) based on MSPB.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
2018
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2<sup>m</sup>) Based on Trinomials.
IEEE Trans. Multi Scale Comput. Syst., 2018
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2<sup>m</sup>).
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems.
IET Comput. Digit. Tech., 2018
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field.
IEEE Access, 2018
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
2017
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IET Inf. Secur., 2017
Gaussian normal basis multiplier over GF(2<sup> <i>m</i> </sup>) using hybrid subquadratic-and-quadratic TMVP approach for elliptic curve cryptography.
IET Circuits Devices Syst., 2017
Proceedings of the IEEE 8th International Conference on Awareness Science and Technology, 2017
Hardware implementation of double basis multiplier using TMVP approach over GF (2<sup>m</sup>).
Proceedings of the IEEE 8th International Conference on Awareness Science and Technology, 2017
2016
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2<sup>m</sup>) Using Generalized (a, b)-Way Karatsuba Algorithm".
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2015
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2<sup>m</sup>) Using Symmetric TMVP and Block Recombination Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2<sup>m</sup>) Using Generalized (a, b)-Way Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Int. J. Ad Hoc Ubiquitous Comput., 2015
Subquadratic space complexity Gaussian normal basis multipliers over GF(2<sup>m</sup>) based on Dickson-Karatsuba decomposition.
IET Circuits Devices Syst., 2015
Efficient subquadratic parallel multiplier based on modified SPB of GF(2<sup>m</sup>).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the Genetic and Evolutionary Computing, 2015
Proceedings of the Genetic and Evolutionary Computing, 2015
Proceedings of the Genetic and Evolutionary Computing, 2015
Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination.
Proceedings of the Genetic and Evolutionary Computing, 2015
Proceedings of the Genetic and Evolutionary Computing, 2015
2014
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2014
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Computers, 2014
A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model.
IEEE Trans. Computers, 2014
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2<sup>m</sup>) using Hankel matrix and Karatsuba algorithm.
IET Inf. Secur., 2013
Proceedings of the Second International Conference on Robot, Vision and Signal Processing, 2013
Proceedings of the Genetic and Evolutionary Computing, 2013
Proceedings of the Genetic and Evolutionary Computing, 2013
2012
Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation.
J. Signal Process. Syst., 2012
IET Inf. Secur., 2012
Palindromic-like representation for Gaussian normal basis multiplier over GF(2<sup>m</sup>) with odd type t.
IET Inf. Secur., 2012
IET Inf. Secur., 2012
Proceedings of the 2012 International Symposium on Biometrics and Security Technologies, 2012
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012
2011
Multiplexer implementation of low-complexity polynomial basis multiplier in GF(m<sup>2</sup>) using all one polynomial.
Inf. Process. Lett., 2011
Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2<sup>m</sup>).
Int. J. Auton. Adapt. Commun. Syst., 2011
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula.
Proceedings of the Fifth International Conference on Genetic and Evolutionary Computing, 2011
Proceedings of the Fifth International Conference on Genetic and Evolutionary Computing, 2011
2010
Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2<sup><i>m</i></sup>) Using Double Parity Prediction Scheme.
J. Signal Process. Syst., 2010
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2<sup>m</sup>) Using Multiple Parity Prediction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2<sup>m</sup>).
Integr., 2010
Concurrent error detection in semi-systolic dual basis multiplier over GF(2<sup>m</sup>) using self-checking alternating logic.
IET Circuits Devices Syst., 2010
Comput. Electr. Eng., 2010
Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2<sup>m</sup>).
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2010
Proceedings of the International Conference on Computational Aspects of Social Networks, 2010
Proceedings of the International Conference on Computational Aspects of Social Networks, 2010
Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach.
Proceedings of the 24th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2010
2009
Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m).
IEEE Trans. Computers, 2009
Concurrent error detection and correction in dual basis multiplier over GF(2<sup>m</sup>).
IET Circuits Devices Syst., 2009
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2009
Scalable Serial-parallel Multiplier over GF(2<sup>m</sup>) by Hierarchical Pre-reduction and Input Decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
An optimized design for serial-parallel finite field multiplication over <i>GF</i>(2<sup><i>m</i></sup>) based on all-one polynomials.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2<sup>m</sup>) Under Polynomial Basis and Normal Basis Representations.
J. Signal Process. Syst., 2008
Integr., 2008
Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2<sup><i>m</i></sup>) Using Toeplitz Matrix-Vector Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Comput. Electr. Eng., 2008
Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2<sup>m</sup>).
Proceedings of the 5th International Conference on Mobile Technology, 2008
Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
2007
J. Comput. Sci. Technol., 2007
Scalable and systolic Montgomery multiplier over GF(2<sup>m</sup>) generated by trinomials.
IET Circuits Devices Syst., 2007
Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2<sup>m</sup>).
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007
2006
Low-Complexity Bit-Parallel Multiplier over GF(2<sup>m</sup>) Using Dual Basis Representation.
J. Comput. Sci. Technol., 2006
Concurrent Error Detection in Montgomery Multiplication over <i>GF</i>(2<sup><i>m</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2<sup><i>m</i></sup>).
J. Electron. Test., 2006
Proceedings of the IEEE International Conference on Systems, 2006
New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2<sup>m</sup>).
IEEE Trans. Computers, 2005
Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2<sup><i>m</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2<sup><i>m</i></sup>).
J. Electron. Test., 2005
Multiplexer-based double-exponentiation for normal basis of GF(2<sup><i>m</i></sup>).
Comput. Secur., 2005
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm.
Comput. Electr. Eng., 2005
2004
Low-complexity linear array multiplier for normal basis of type-II.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004
2003
Low-Latency Bit-Parallel Systolic Multiplier for Irreducible x<sup>m</sup> + x<sup>n</sup> + 1 with <i>GCD</i>(<i>m</i>, <i>n</i>) = 1.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.
IEEE Trans. Computers, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001