Meng Liu

According to our database, Meng Liu authored at least 11 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

PttAcc: Pipeline-Based Taylor Expansion Fitting Arctangent Angle Hardware Accelerator Design for Descriptor Duty in ORB-SLAM System.

Meng Liu, Fei Xiao, Ruijie Wang, Peiyuan Wan, Zhijie Chen, Dejian Li, Chongfei Shen

IEEE Embed. Syst. Lett., April, 2025

Clock mesh synthesis through dynamic programming with physical parameters consideration.

Dejian Li, Jie Gan, Chongfei Shen, Qi Chen, Lixin Yang, Sihai Qiu, Xin Jin, Tiantian Wu, Zhijie Chen, Meng Liu

Integr., 2025

2024

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm.

Meng Liu, Shuai Li, Fei Xiao, Ruijie Wang, Chunxue Liu, Liang Wang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems.

Dejian Li, Xi Feng, Chongfei Shen, Qi Chen, Lixin Yang, Sihai Qiu, Xin Jin, Meng Liu

IEEE Embed. Syst. Lett., December, 2023

2022

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor.

Meng Liu

IEICE Electron. Express, 2022

2021

An Approximate Symmetry Clock Tree Design with Routing Topology Prediction.

Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress.

Meng Liu

Proceedings of the CODES/ISSS 2021, 2021

2020

HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System.

Renwei Li, Junning Wu, Meng Liu, Zuding Chen, Shengang Zhou, Shanggong Feng

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2017

A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis.

Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang

IEICE Electron. Express, 2017

Obstacle-aware symmetrical clock tree construction.

Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Optimization of clock mesh based on wire sizing variation.

Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang

Proceedings of the International SoC Design Conference, 2017