Liang Wang

Orcid: 0000-0002-0061-5502

Affiliations:
  • Beijing Microelectronics Technology Institute, China


According to our database1, Liang Wang authored at least 7 papers between 2007 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Toward Exploring Fault-Tolerant Neural Architectures: A Hierarchical Codesign Optimization Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

A Highly Reliable RRAM-Based 12T2R NVSRAM Architecture With Dual-Layer ECC.
IEEE Trans. Very Large Scale Integr. Syst., January, 2026

2024
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2021
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2017
High energy proton and heavy ion induced single event transient in 65-nm CMOS technology.
Sci. China Inf. Sci., 2017

2007
An SEU-Tolerant Programmable Frequency Divider.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007


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