Peiyuan Wan

Orcid: 0000-0003-4875-6432

According to our database1, Peiyuan Wan authored at least 29 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A fast-response RBCOT buck converter with second-order differential and integrator compensation based on FVF.
Microelectron. J., 2024

A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Design of analog front-end integrated circuit of tactile sensor for human-machine interface.
Integr., November, 2023

A 4-Channel Neural Stimulation IC Design With Charge Balancing and Multiple Current Output Modes.
IEEE Trans. Biomed. Circuits Syst., October, 2023

A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application.
IEEE Trans. Biomed. Circuits Syst., October, 2023

A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration.
IEICE Electron. Express, 2023

A Fast Bioimpedance Measurement Chip Design Using Dynamic Current.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A Bio-Impedance Measurement Chip Design with AC Current Outputs.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer.
IEICE Electron. Express, 2022

Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique.
IEICE Electron. Express, 2022

A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine Interface.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 4-Channel Neural Stimulation IC Design with Charge Balancing and Exponential Current Output.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A 1.65 mW 2.8 GHz Dual-Loops Class-C VCO Achieving 189 dBc/Hz FoM.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Design of an Exponential Current Generator for Neural Stimulation.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 4x folding voltage-to-time converter with adjustable conversion gain and offset for time-based ADC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019
Non-Ideal Issues Analysis in a Fully Passive Noise Shaping SAR ADC.
IEICE Trans. Electron., 2019

2015
Design and testing of CMOS compatible EEPROM.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A digitally calibrated low-power ring oscillator.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS.
J. Circuits Syst. Comput., 2013

2011
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration.
IEEE J. Solid State Circuits, 2011

A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A High Linearity 6<sup>th</sup>-order active R-MOSFET-C band-pass filter for power-line communication.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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