Mengdi Wang

Orcid: 0000-0002-7012-2308

According to our database1, Mengdi Wang authored at least 17 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2025
DNA: A General Dynamic Neural Network Accelerator.
IEEE Trans. Computers, September, 2025

ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning.
CoRR, July, 2025

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework.
CoRR, January, 2025

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

COMET: Towards Practical W4A4KV4 LLMs Serving.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
COMET: Towards Partical W4A4KV4 LLMs Serving.
CoRR, 2024

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
ChipGPT: How far are we from natural language hardware design.
CoRR, 2023

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Deep Learning Compiler Optimization on Multi-Chiplet Architecture.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2021
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


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