Cheng Liu

Orcid: 0000-0002-5542-7306

Affiliations:

Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong (PhD 2016)

According to our database¹, Cheng Liu authored at least 67 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

PDG: A Prefetcher for Dynamic Graph Updating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., March, 2024

2023

Soft Error Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Statistical Modeling of Soft Error Influence on Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., July, 2023

Network Pruning for Bit-Serial Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., March, 2023

On-Line Fault Protection for ReRAM-Based Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

A Framework for Neural Network Architecture and Compile Co-optimization.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2023

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs.

[BibT_eX]

[DOI]

CoRR, 2023

Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

CoRR, 2023

Deep Learning Accelerator in Loop Reliability Evaluation for Autonomous Driving.

[BibT_eX]

[DOI]

Haitong Huang

Cheng Liu

CoRR, 2023

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing.

[BibT_eX]

[DOI]

CoRR, 2023

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Variation Enhanced Attacks Against RRAM-based Neuromorphic Computing System.

[BibT_eX]

[DOI]

CoRR, 2023

MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-Linear Functions.

[BibT_eX]

[DOI]

Proceedings of the Eleventh International Conference on Learning Representations, 2023

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach

[BibT_eX]

[DOI]

Xiaowei Li

Guihai Yan

Cheng Liu

Springer, ISBN: 978-981-19-8550-8, 2023

2022

Taming Process Variations in CNFET for Efficient Last-Level Cache Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems.

[BibT_eX]

[DOI]

Benjamin Chen Ming Choong

J. Syst. Archit., 2022

Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

CoRR, 2022

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Winograd convolution: a perspective from fault tolerance.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

VStore: in-storage graph based vector search accelerator.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Processing-in-SRAM acceleration for ultra-low power visual 3D perception.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Taming Process Variations in CNFET for Efficient Last Level Cache Design.

[BibT_eX]

[DOI]

CoRR, 2021

Energy-Efficient Accelerator Design for Deformable Convolution Networks.

[BibT_eX]

[DOI]

CoRR, 2021

GLIST: Towards In-Storage Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 2021 USENIX Annual Technical Conference, 2021

CHaNAS: coordinated search for network architecture and scheduling policy.

[BibT_eX]

[DOI]

Proceedings of the LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, 2021

NASA: Accelerating Neural Network Design with a NAS Processor.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 2021

MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

GCiM: A Near-Data Processing Accelerator for Graph Construction.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

BitPruner: Network Pruning for Bit-serial Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

A Survey on Graph Processing Accelerators: Challenges and Opportunities.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2019

Squeezing the Last MHz for CNN Acceleration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Exploring emerging CNFET for efficient last level cache design.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

FCN-engine: accelerating deconvolutional layers in classic CNN processors.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2015

Economizing TSV Resources in 3-D Network-on-Chip Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

2011

A resilient on-chip router design through data path salvaging.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Cheng Liu

Timeline

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