Cangyuan Li

Orcid: 0000-0002-7193-464X

According to our database1, Cangyuan Li authored at least 13 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL.
CoRR, March, 2026

TriMoE: Augmenting GPU with AMX-Enabled CPU and DIMM-NDP for High-Throughput MoE Inference via Offloading.
CoRR, March, 2026

FHEx: Transforming Generic Compute Chips into Secure FHE Engines via a Hardware-software Co-designed Framework.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models.
ACM Trans. Design Autom. Electr. Syst., November, 2025

A data-centric chip design agent framework for Verilog code generation.
ACM Trans. Design Autom. Electr. Syst., November, 2025

ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning.
CoRR, July, 2025

Large Processor Chip Model.
CoRR, June, 2025

2024
GTA: a new General Tensor Accelerator with Better Area Efficiency and Data Reuse.
CoRR, 2024

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Can We Trust Race Prediction?
CoRR, 2023

APPEND: Rethinking ASIP Synthesis in the Era of AI.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
GLIST: Towards In-Storage Graph Learning.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021


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