Michael A. Turi

Orcid: 0000-0002-9171-5305

According to our database1, Michael A. Turi authored at least 13 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Scripts for Easier Use of Spice (SEUS): A Perl script package for simulating and creating batches of circuit netlists for Monte Carlo simulations when using Ngspice or Ngspice-based simulators.
J. Open Source Softw., 2020

2017
Full-V<sub>DD</sub> and near-threshold performance of 8T FinFET SRAM cells.
Integr., 2017

An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

2015
Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
An evaluation of 6T and 8T FinFET SRAM cell leakage currents.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2012
FinFET 3T and 3T1D dynamic RAM cells.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2010
Low power SRAM cell design for FinFET and CNTFET technologies.
Proceedings of the International Green Computing Conference 2010, 2010

2009
Decreasing energy consumption in address decoders by means of selective precharge schemes.
Microelectron. J., 2009

2008
High-Performance Low-Power Selective Precharge Schemes for Address Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

High-performance low-power AND and Sense-Amp address decoders with selective precharging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


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