Michael Choi
Orcid: 0000-0003-3525-9613
According to our database1,
Michael Choi
authored at least 36 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3<sup>rd</sup>-Order SAR-Assisted CT DSM with 1-0 MASH and DNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
IEEE Trans. Image Process., 2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 0.65V 1316µm<sup>2</sup>Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration.
IEEE J. Solid State Circuits, 2021
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Recent Developments of the Space Exploration Synthetic Aperture Radar (SESAR) for Planetary Science Missions.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
2018
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits, 2018
J. Econ. Theory, 2018
A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
J. Econ. Theory, 2017
2015
IEEE J. Solid State Circuits, 2015
2014
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Close-proximity, real-time thermoacoustic sensors: Design, characterization, and testing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2001
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000