Michael A. Inerfield

According to our database1, Michael A. Inerfield authored at least 7 papers between 2000 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014


2008
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture.
IEEE J. Solid State Circuits, 2006

A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2000
A SPICE model for a novel brushless adjustable-speed drive.
IEEE Trans. Ind. Electron., 2000


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