Asad A. Abidi

Orcid: 0000-0002-7064-0738

Affiliations:
  • UCLA


According to our database1, Asad A. Abidi authored at least 101 papers between 1992 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1996, "For contributions to the design of high-frequency MOS analog integrated circuits.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Second-Order Transimpedance Amplifiers in Mixer-First Receivers: Design for Optimum Blocker Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

2022
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application.
IEEE J. Solid State Circuits, 2022

Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation.
IEEE J. Solid State Circuits, 2022

Envelope Tracking Supply Modulator with Trellis-Search-Based Switching and 160-MHz Capability.
IEEE J. Solid State Circuits, 2022

A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Approximate Equivalent Circuits to Understand Tradeoffs in Geometry of On-Chip Inductors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
Proceedings of the 47th ESSCIRC 2021, 2021

Envelope-Tracking Supply Modulator with Trellis Search-Based Switching and 160MHz Capability.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK Data Link.
IEEE J. Solid State Circuits, 2020

2019
Analysis and Design of Regenerative Comparators for Low Offset and Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils.
IEEE J. Solid State Circuits, 2019

A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit.
IEICE Trans. Electron., 2018

Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

22.7 An inductively-coupled wireless power-transfer system that is immune to distance and load variations.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2014
An LTV Analysis of the Frequency Translational Noise-Cancelling Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Understanding the regenerative comparator circuit.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Multiband RF Antenna Duplexer on CMOS: Design and Performance.
IEEE J. Solid State Circuits, 2013

2012
A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications.
IEEE J. Solid State Circuits, 2012

A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS.
IEEE J. Solid State Circuits, 2011

A low-power wideband polar transmitter for 3G applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Beyond the horizon: The next 10x reduction in power - Challenges and solutions.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Phase Noise in <i>LC</i> Oscillators: A Phasor-Based Analysis of a General Result and of Loaded Q.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

The Spectrum of a Noisy Free-Running Oscillator Explained by Random Frequency Pulling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Noise in Current-Commutating Passive FET Mixers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A Second-Order Antialiasing Prefilter for a Software-Defined Radio Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Second-Order Intermodulation in Current-Commutating Passive FET Mixers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution.
IEEE J. Solid State Circuits, 2009

All-Digital Outphasing Modulator for a Software-Defined Transmitter.
IEEE J. Solid State Circuits, 2009

A tunable integrated duplexer with 50dB isolation in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Analysis of First-Order Anti-Aliasing Integration Sampler.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers.
IEEE J. Solid State Circuits, 2008

A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue.
IEEE J. Solid State Circuits, 2008

An Outphasing Power Amplifier for a Software-Defined Radio Transmitter.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking.
IEEE J. Solid State Circuits, 2007

The Path to the Software-Defined Radio Receiver.
IEEE J. Solid State Circuits, 2007

Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS.
IEEE J. Solid State Circuits, 2006

Software-defined radio receiver: dream to reality.
IEEE Commun. Mag., 2006

An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A 1 GHz CMOS analog front-end for a generalized PRML read channel.
IEEE J. Solid State Circuits, 2005

A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for mode-2 MB-OFDM UWB communication.
IEEE J. Solid State Circuits, 2005

A second-order anti-aliasing prefilter for an SDR receiver.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A 6.5 GHz wideband CMOS low noise amplifier for multi-band use.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Analog behavioral modeling: fantasy, fad, or foundation for the future?
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Phase noise in inverter-based & differential CMOS ring oscillators.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
In Memoriam.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Spectral spurs due to quantization in Nyquist ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Signal folding in A/D converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network.
IEEE J. Solid State Circuits, 2004

RF CMOS comes of age.
IEEE J. Solid State Circuits, 2004

Noise in passive FET mixers: a simple physical model.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Spatial filtering in flash A/D converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A merged CMOS LNA and mixer for a WCDMA receiver.
IEEE J. Solid State Circuits, 2003

Demodulators for a zero-IF Bluetooth receiver.
IEEE J. Solid State Circuits, 2003

Varactor characteristics, oscillator tuning curves, and AM-FM conversion.
IEEE J. Solid State Circuits, 2003

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2003

Low power demodulators with phase quantization for a zero-IF Bluetooth receiver.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver.
IEEE J. Solid State Circuits, 2002

2001
A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel.
IEEE J. Solid State Circuits, 2001

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2001

A filtering technique to lower LC oscillator phase noise.
IEEE J. Solid State Circuits, 2001

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2001

Adaptive analog IF signal processor for a wide-band CMOS wireless receiver.
IEEE J. Solid State Circuits, 2001

CMOS mixers and polyphase filters for large image rejection.
IEEE J. Solid State Circuits, 2001

Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICE.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Power-conscious design of wireless circuits and systems.
Proc. IEEE, 2000

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR.
IEEE J. Solid State Circuits, 2000

A 4.5-mW 900-MHz CMOS receiver for wireless paging.
IEEE J. Solid State Circuits, 2000

Noise in RF-CMOS mixers: a simple physical model.
IEEE J. Solid State Circuits, 2000

A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver.
IEEE J. Solid State Circuits, 2000

A 2.4-GHz low-IF receiver for wideband WLAN in 6-μm CMOS-architecture and front-end.
IEEE J. Solid State Circuits, 2000

Physical processes of phase noise in differential LC oscillators.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
De-embedding the noise figure of differential amplifiers.
IEEE J. Solid State Circuits, 1999

CMOS wireless transceivers: the new wave.
IEEE Commun. Mag., 1999

Low power RF integrated circuits: principles and practice.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

An ultralow power single-chip CMOS 900 MHz receiver for wireless paging.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

A wideband tunable CMOS channel-select filter for a low-IF wireless receiver.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. II. Receiver design.
IEEE J. Solid State Circuits, 1998

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. I. Architecture and transmitter design.
IEEE J. Solid State Circuits, 1998

An analog EPR4 read channel with an FDTS detector.
Proceedings of the 1998 IEEE International Conference on Communications, 1998

Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver.
Proceedings of the 35th Conference on Design Automation, 1998

RF-CMOS oscillators with switched tuning.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
A 10-b, 100-MS/s CMOS A/D converter.
IEEE J. Solid State Circuits, 1997

A CMOS channel-select filter for a direct-conversion wireless receiver.
IEEE J. Solid State Circuits, 1997

1996
A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver.
IEEE J. Solid State Circuits, 1996

A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels.
IEEE J. Solid State Circuits, 1996

1995
Direct-conversion radio transceivers for digital communications.
IEEE J. Solid State Circuits, December, 1995

Low-power radio-frequency ICs for portable communications.
Proc. IEEE, 1995

1994
A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels.
IEEE J. Solid State Circuits, April, 1994

1993
A table lookup FET model for accurate analog circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A Low Power Analog CMOS Vector Quantizer.
Proceedings of the IEEE Data Compression Conference, 1993

1992
A Simple Continuous-Time Equalizer for Use in Magnetic Storage Read Channels.
IEEE J. Sel. Areas Commun., 1992


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