Michael W. Beattie

According to our database1, Michael W. Beattie authored at least 15 papers between 1997 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2005
Spatially distributed 3D circuit models.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Parasitics extraction with multipole refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2002
On-chip induction modeling: basics and advanced methods.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.
Proceedings of the 2002 Design, 2002

On-Chip Inductance Models: 3D or Not 3D?
Proceedings of the 2002 Design, 2002

On the efficacy of simplified 2D on-chip inductance models.
Proceedings of the 39th Design Automation Conference, 2002

2001
Equipotential shells for efficient inductance extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Efficient inductance extraction via windowing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Modeling Magnetic Coupling for On-Chip Interconnect.
Proceedings of the 38th Design Automation Conference, 2001

Inductance 101: Modeling and Extraction.
Proceedings of the 38th Design Automation Conference, 2001

2000
Hierarchical Interconnect Circuit Models.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Error bounds for capacitance extraction via window techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

IC Analyses Including Extracted Inductance Models.
Proceedings of the 36th Conference on Design Automation, 1999

1997
Bounds for BEM Capacitance Extraction.
Proceedings of the 34st Conference on Design Automation, 1997


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