Lawrence T. Pileggi

According to our database1, Lawrence T. Pileggi authored at least 225 papers between 1988 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to simulation and modeling of integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2018
Application and Product-Volume-Specific Customization of BEOL Metal Pitch.
IEEE Trans. VLSI Syst., 2018

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs.
IEEE Trans. on Circuits and Systems, 2018

StreamCast: Fast and Online Mining of Power Grid Time Sequences.
Proceedings of the 2018 SIAM International Conference on Data Mining, 2018

GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2018

An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph.
Proceedings of the 27th ACM International Conference on Information and Knowledge Management, 2018

2017
PowerCast: Mining and Forecasting Power Grid Sequences.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2017

A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Virtual characterization for exhaustive DFM evaluation of logic cell libraries.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Linear load model for robust power system analysis.
Proceedings of the 2017 IEEE PES Innovative Smart Grid Technologies Conference Europe, 2017

Algorithm and hardware co-optimized solution for large SpMV problems.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration.
Integration, 2016

Steady-state analysis of power system harmonics using equivalent split-circuit models.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference Europe, 2016

Unified power system analyses and models using equivalent circuit formulation.
Proceedings of the 2016 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2016

On the design of phase locked loop oscillatory neural networks: Mitigation of transmission delay effects.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

3D DRAM based application specific hardware accelerator for SpMV.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016

Extended statistical element selection: a calibration method for high resolution in analog/RF designs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC.
IEEE Trans. on Circuits and Systems, 2015

Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
IEEE Computer, 2015

Enabling portable energy efficiency with memory accelerated library.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

An RRAM-based Oscillatory Neural Network.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Analog neuromorphic computing enabled by multi-gate programmable resistive devices.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A synthesis methodology for application-specific logic-in-memory designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.
IEEE Trans. on Circuits and Systems, 2014

A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI.
J. Solid-State Circuits, 2014

Sub-20 nm design technology co-optimization for standard cell logic.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Efficient and secure intellectual property (IP) design with split fabrication.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Building trusted ICs using split fabrication.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Joint invariant estimation of RF impairments for reconfigurable Radio Frequency(RF) front-end.
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 8-12, 2014, 2014

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A wideband RF receiver with >80 dB harmonic rejection ratio.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Toward efficient programming of reconfigurable radio frequency (RF) receivers.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation.
Signal Processing Systems, 2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. on Circuits and Systems, 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
J. Solid-State Circuits, 2013

Formal verification of phase-locked loops using reachability analysis and continuization.
Commun. ACM, 2013

All-magnetic analog associative memory.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Fully-digital oscillatory associative memories enabled by non-volatile logic.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Neurocomputing and associative memories based on ovenized aluminum nitride resonators.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
A Smart Memory Accelerated Computed Tomography Parallel Backprojection.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

Cost-effective smart memory implementation for parallel backprojection in computed tomography.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Statistical design and optimization for adaptive post-silicon tuning of MEMS filters.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012


Design Automation Framework for Application-Specific Logic-in-Memory Blocks.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs.
J. Solid-State Circuits, 2011

Formal verification of phase-locked loops using reachability analysis and continuization.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Post-silicon calibration of analog CMOS using phase-change memory cells.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Indirect phase noise sensing for self-healing voltage controlled oscillators.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Reducing variability in chip-multiprocessors with adaptive body biasing.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Statistical modeling and post manufacturing configuration for scaled analog CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Efficient statistical analysis of read timing failures in SRAM circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

SRAM parametric failure analysis.
Proceedings of the 46th Design Automation Conference, 2009

Creating an affordable 22nm node using design-lithography co-optimization.
Proceedings of the 46th Design Automation Conference, 2009

2008
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proceedings of the IEEE, 2008

Automated Testability Enhancements for Logic Brick Libraries.
Proceedings of the Design, Automation and Test in Europe, 2008

A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Mismatch analysis and statistical design at 65 nm and below.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Asymptotic Probability Extraction for Nonnormal Performance Distributions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Robust Analog/RF Circuit Design With Projection-Based Performance Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Parameterized Macromodeling for Analog System-Level Design Exploration.
Proceedings of the 44th Design Automation Conference, 2007

Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks.
Proceedings of the 44th Design Automation Conference, 2007

Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
IC thermal simulation and modeling via efficient multigrid-based approaches.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Statistical Performance Modeling and Optimization.
Foundations and Trends in Electronic Design Automation, 2006

Design Methodology of Regular Logic Bricks for Robust Integrated Circuits.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.
Proceedings of the 43rd Design Automation Conference, 2006

Architecture-aware FPGA placement using metric embedding.
Proceedings of the 43rd Design Automation Conference, 2006

Active On-Die Suppression of Power Supply Noise.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Compact reduced-order modeling of weakly nonlinear analog and RF circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Temperature-Dependent Optimization of Cache Leakage Power Dissipation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Performance-centering optimization for system-level analog design exploration.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Projection-based performance modeling for inter/intra-die variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.
Proceedings of the 2005 Design, 2005

Specification Test Compaction for Analog Circuits and MEMS.
Proceedings of the 2005 Design, 2005

Correlation-aware statistical timing analysis with non-gaussian delay distributions.
Proceedings of the 42nd Design Automation Conference, 2005

OPERA: optimization with ellipsoidal uncertainty for robust analog IC design.
Proceedings of the 42nd Design Automation Conference, 2005

Design methodology for IC manufacturability based on regular logic-bricks.
Proceedings of the 42nd Design Automation Conference, 2005

A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Parasitics extraction with multipole refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Efficient full-chip thermal modeling and analysis.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient harmonic balance simulation using multi-level frequency decomposition.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Asymptotic probability extraction for non-normal distributions of circuit performance.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Robust analog/RF circuit design with projection-based posynomial modeling.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A power aware system level interconnect design methodology for latency-insensitive systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Exploring Logic Block Granularity for Regular Fabrics.
Proceedings of the 2004 Design, 2004

An Interconnect Channel Design Methodology for High Performance Integrated Circuits.
Proceedings of the 2004 Design, 2004

ORACLE: optimization with recourse of analog circuits including layout extraction.
Proceedings of the 41th Design Automation Conference, 2004

A frequency relaxation approach for analog/RF system-level simulation.
Proceedings of the 41th Design Automation Conference, 2004

STAC: statistical timing analysis with correlation.
Proceedings of the 41th Design Automation Conference, 2004

Routing architecture exploration for regular fabrics.
Proceedings of the 41th Design Automation Conference, 2004

CHIME: coupled hierarchical inductance model evaluation.
Proceedings of the 41th Design Automation Conference, 2004

2003
Global and local congestion optimization in technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Efficient per-nonlinearity distortion analysis for analog and RF circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Electrical Modeling of Integrated-Package Power and Ground Distributions.
IEEE Design & Test of Computers, 2003

Power Comparison of Throughput Optimized IC Busses.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

An architectural exploration of via patterned gate arrays.
Proceedings of the 2003 International Symposium on Physical Design, 2003

A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A fast simulation approach for inductive effects of VLSI interconnects.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Bounding the efforts on congestion optimization for physical synthesis.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Noise Macromodel for Radio Frequency Integrated Circuits.
Proceedings of the 2003 Design, 2003

Heterogeneous Programmable Logic Block Architectures.
Proceedings of the 2003 Design, 2003

Exploring regular fabrics to optimize the performance-cost trade-off.
Proceedings of the 40th Design Automation Conference, 2003

NORM: compact model order reduction of weakly nonlinear systems.
Proceedings of the 40th Design Automation Conference, 2003

Analog and RF circuit macromodels for system-level analysis.
Proceedings of the 40th Design Automation Conference, 2003

Fast, cheap and under control: the next implementation fabric.
Proceedings of the 40th Design Automation Conference, 2003

Nonlinear distortion analysis via linear-centric models.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A frequency separation macromodel for system-level simulation of RF circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation.
VLSI Design, 2002

On-chip induction modeling: basics and advanced methods.
IEEE Trans. VLSI Syst., 2002

An analysis of the wire-load model uncertainty problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

TETA: transistor-level waveform evaluation for timing analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Time-Domain Simulation of Variational Interconnect Models.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Understanding and addressing the impact of wiring congestion during technology mapping.
Proceedings of 2002 International Symposium on Physical Design, 2002

Robust and passive model order reduction for circuits containing susceptance elements.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Throughput-driven IC communication fabric synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Modular, Fabric-Specific Synthesis for Programmable Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2002

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.
Proceedings of the 2002 Design, 2002

Congestion-Aware Logic Synthesis.
Proceedings of the 2002 Design, 2002

On-Chip Inductance Models: 3D or Not 3D?
Proceedings of the 2002 Design, 2002

A Linear-Centric Modeling Approach to Harmonic Balance Analysis.
Proceedings of the 2002 Design, 2002

A Linear-Centric Simulation Framework for Parametric Fluctuations.
Proceedings of the 2002 Design, 2002

Modeling and analysis of regular symmetrically structured power/ground distribution networks.
Proceedings of the 39th Design Automation Conference, 2002

On the efficacy of simplified 2D on-chip inductance models.
Proceedings of the 39th Design Automation Conference, 2002

2001
Equipotential shells for efficient inductance extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

RC(L) interconnect sizing with second order considerations via posynomial programming.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Overcoming wireload model uncertainty during physical design.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Efficient inductance extraction via windowing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Min/max On-Chip Inductance Models and Delay Metrics.
Proceedings of the 38th Design Automation Conference, 2001

Modeling Magnetic Coupling for On-Chip Interconnect.
Proceedings of the 38th Design Automation Conference, 2001

Inductance 101: Modeling and Extraction.
Proceedings of the 38th Design Automation Conference, 2001

False Coupling Interactions in Static Timing Analysis.
Proceedings of the 38th Design Automation Conference, 2001

2000
Hierarchical Interconnect Circuit Models.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Impact of interconnect variations on the clock skew of a gigahertz microprocessor.
Proceedings of the 37th Conference on Design Automation, 2000

Design closure (panel session): hope or hype?
Proceedings of the 37th Conference on Design Automation, 2000

TACO: timing analysis with coupling.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Error bounds for capacitance extraction via window techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Practical considerations for passive reduction of RLC circuits.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Model Order-Reduction of RC(L) Interconnect Including Variational Analysis.
Proceedings of the 36th Conference on Design Automation, 1999

IC Analyses Including Extracted Inductance Models.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers.
IEEE Trans. VLSI Syst., 1998

EWA: efficient wiring-sizing algorithm for signal nets and clock nets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Timing metrics for physical design of deep submicron technologies.
Proceedings of the 1998 International Symposium on Physical Design, 1998

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Determination of worst-case aggressor alignment for delay calculation.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models.
Proceedings of the 35th Conference on Design Automation, 1998

PRIMO: Probability Interpretation of Moments for Delay Calculation.
Proceedings of the 35th Conference on Design Automation, 1998

TETA: Transistor-Level Engine for Timing Analysis.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

The Elmore delay as a bound for RC trees with generalized input signals.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Transmission line synthesis via constrained multivariable optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

EWA: exact wiring-sizing algorithm.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Clustering and Load Balancing for Buffered Clock Tree Synthesis.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

CMOS Gate Delay Models for General RLC Loading.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

PRIMA: passive reduced-order interconnect macromodeling algorithm.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A hierarchical decomposition methodology for multistage clock circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

SPIE: Sparse Partial Inductance Extraction.
Proceedings of the 34st Conference on Design Automation, 1997

Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling.
Proceedings of the 34st Conference on Design Automation, 1997

Bounds for BEM Capacitance Extraction.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Post-processing of clock trees via wiresizing and buffering for robust design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Domain characterization of transmission line models and analyses.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Performance computation for precharacterized CMOS gates with RC loads.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response.
Proceedings of the 33st Conference on Design Automation, 1996

A Sparse Image Method for BEM Capacitance Extraction.
Proceedings of the 33st Conference on Design Automation, 1996

RC-Interconnect Macromodels for Timing Simulation.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Coping with RC(L) interconnect design headaches.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A sequential quadratic programming approach to concurrent gate and wire sizing.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Generating sparse partial inductance matrices with guaranteed stability.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Constrained multivariable optimization of transmission lines with general topologies.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.
Proceedings of the 32st Conference on Design Automation, 1995

Transmission Line Synthesis.
Proceedings of the 32st Conference on Design Automation, 1995

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals.
Proceedings of the 32st Conference on Design Automation, 1995

1994
RICE: rapid interconnect circuit evaluation using AWE.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Time-domain macromodels for VLSI interconnect analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Domain Characterization of Transmission Line Models for Efficient Simulation.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

RC interconnect synthesis-a moment fitting approach.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

OTTER: Optimal Termination of Transmission Lines Excluding Radiation.
Proceedings of the 31st Conference on Design Automation, 1994

A Gate-Delay Model for high-Speed CMOS Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
AWE macromodels of VLSI interconnect for circuit simulation.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

ETA: electrical-level timing analysis.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation.
Proceedings of the 29th Design Automation Conference, 1992

1991
Evaluating RC-Interconnect Using Moment-Matching Approximations.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

RICE: Rapid Interconnect Circuit Evaluator.
Proceedings of the 28th Design Automation Conference, 1991

1990
Asymptotic waveform evaluation for timing analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Efficient Final Placement Based on Nets-as-Points.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

AWEsim: Asymptotic Waveform Evaluation for Timing Analysis.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
A Quadratic Metric with a Simple Solution Scheme for Initial Placement.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


  Loading...