Milagros Sashikánth

According to our database1, Milagros Sashikánth authored at least 8 papers between 2004 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2006
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A function generator-based reconfigurable system.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004


  Loading...