Ming-Zhang Kuo

According to our database, Ming-Zhang Kuo authored at least 6 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

An RFID Reader Antenna Design with Circular Polarization for Sports-Event and -Timing Applications.

Ming-Zhang Kuo, Tung-Ming Koo, Shih-Chieh Chen, Chia-Hung Chang, Ming-Sing Lin, Chung-I G. Hsu

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2015

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.

Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 4-GHz universal high-frequency on-chip testing platform for IP validation.

Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.

Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.

Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm² per MB.

Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013