Wei Hwang
According to our database1,
Wei Hwang
authored at least 113 papers
between 1994 and 2022.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2001, "For contributions to high density cell technology and high speed Dynamic Random Access Memory design.".
Timeline
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Bibliography
2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks.
IEEE Open J. Circuits Syst., 2021
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks.
Proceedings of the 18th International SoC Design Conference, 2021
2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications.
Proceedings of the VLSI Design, Automation and Test, 2015
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications.
IEEE Trans. Biomed. Circuits Syst., 2014
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Energy-efficient configurable discrete wavelet transform for neural sensing applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation.
J. Low Power Electron., 2013
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Through-silicon-via-based double-side integrated microsystem for neural sensing applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Design and Iso-Area V<sub>min</sub> Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
J. Low Power Electron., 2012
A 0.4 V 520 nW 990 <i>μ</i>m<sup>2</sup> Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS.
J. Low Power Electron., 2012
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks.
J. Electr. Comput. Eng., 2012
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation.
Proceedings of the IEEE 25th International SOC Conference, 2012
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron., 2010
Power noise suppression technique using active decoupling capacitor for TSV 3D integration.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
In-situ self-aware adaptive power control system with multi-mode power gating network.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
"Green" micro-architecture and circuit co-design for ternary content addressable memory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.
J. VLSI Signal Process., 2004
2003
IBM J. Res. Dev., 2003
2002
Multiplier architecture power consumption characterization for low-power DSP applications.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE J. Solid State Circuits, 2000
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
1999
IEEE J. Solid State Circuits, 1999
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability.
IEEE J. Solid State Circuits, 1999
Design Considerations and Implementation of a High Performance Dynamic Register File.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
1998
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems.
IEEE J. Solid State Circuits, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1994
IEEE J. Solid State Circuits, July, 1994