Min-Jer Wang

According to our database, Min-Jer Wang authored at least 28 papers between 2008 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Novel Circuit Probing for Tiny Inductor.

Chia-Heng Tsai, Chi-Chang Lai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference in Asia, 2020

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill.

Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference in Asia, 2020

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.

Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

High Quality Test Methodology for Highly Reliable Devices.

Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference, 2019

2017

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.

Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Trans. Computers, 2017

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.

Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Des. Test, 2017

Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO.

Tang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang

Proceedings of the International Test Conference in Asia, 2017

Fan-out wafer level chip scale package testing.

Hao Chen, Hung-Chih Lin, Min-Jer Wang

Proceedings of the International Test Conference in Asia, 2017

2016

A Local Parallel Search Approach for Memory Failure Pattern Identification.

Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Trans. Computers, 2016

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Des. Test, 2016

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.

Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.

Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.

Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta

IEEE J. Solid State Circuits, 2014

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.

Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng

IEEE Des. Test, 2014

A 4-GHz universal high-frequency on-chip testing platform for IP validation.

Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A novel DFT architecture for 3DIC test, diagnosis and repair.

Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS^TM/3D ICs.

Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Redundancy architectures for channel-based 3D DRAM yield improvement.

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2014 International Test Conference, 2014

Wafer Level Chip Scale Package copper pillar probing.

Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2014 International Test Conference, 2014

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.

Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.

Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

3D-IC interconnect test, diagnosis, and repair.

Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch.

Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2013 IEEE International Test Conference, 2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim

Proceedings of the 2013 IEEE International Test Conference, 2013

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm² per MB.

Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS.

Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee

Proceedings of the Symposium on VLSI Circuits, 2012

A memory yield improvement scheme combining built-in self-repair and error correction codes.

Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2012 IEEE International Test Conference, 2012

2008

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS.

Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008