Mingshuo Wang

According to our database1, Mingshuo Wang authored at least 8 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth.
IEICE Electron. Express, 2014

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>.
IEICE Electron. Express, 2014

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A cancellation technique for output-dependent delay differences in high-accuracy DACs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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