Chixiao Chen
Orcid: 0000-0002-5980-4236
According to our database1,
Chixiao Chen
authored at least 64 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Neuromorph. Comput. Eng., December, 2022
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
IEEE Des. Test, 2022
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Integr., 2020
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Exploring the programmability for deep learning processors: from architecture to tensorization.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEICE Electron. Express, 2015
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Electron. Express, 2013
Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011