Miryala Chandra Shekar

According to our database, Miryala Chandra Shekar authored at least 3 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction.

Aakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2022

A 0.009mm², 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs.

Javed S. Gaggatur, Miryala Chandra Shekar, Komal Deshmukh

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021

A 27S/32S DC-balanced line coding scheme for PAM-4 signaling.

Miryala Chandra Shekar, Sandeep Goyal, Shalabh Gupta

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021