Mitchell J. Myjak

Orcid: 0000-0002-3807-3542

According to our database1, Mitchell J. Myjak authored at least 10 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A Frequency-Programmable Miniaturized Radio Frequency Transmitter for Animal Tracking.
Sensors, 2021

2008
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Medium-Grain Cells for Reconfigurable DSP Hardware.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006
Superpipelined reconfigurable hardware for DSP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005
A Symmetric Differential Clock Generator for Bit-Serial Hardware.
Proceedings of the 2005 International Conference on Computer Design, 2005

Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
Pipelined Multipliers for Reconfigurable Hardware.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

H-Tree Interconnection Structure for Reconfigurable DSP Hardware.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
A Two-Level Reconfigurable Architecture for Digital Signal Processing.
Proceedings of the International Conference on VLSI, 2003


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