Mitsuji Ikeda

According to our database, Mitsuji Ikeda authored at least 5 papers between 1985 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Application of a Design for Delay Testability Approach to High Speed Logic LSIs.

Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1993

Sequential circuit test generation by real number simulation.

Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi

Syst. Comput. Jpn., 1993

1992

Sequential Test Generation Based on Real-Value Logic.

Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1989

Enhanced Delay Test Generator for High-Speed Logic LSIs.

Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama

Proceedings of the Proceedings International Test Conference 1989, 1989

1985

Vulnerability of a communication network with a satellite.

Kenichi Hagihara, Toshimitsu Masuzawa, Nobuki Tokura, Mitsuji Ikeda

Syst. Comput. Jpn., 1985