Kazumi Hatayama

According to our database¹, Kazumi Hatayama authored at least 54 papers between 1989 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2023

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2023

2022

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies.

[BibT_eX]

[DOI]

J. Electron. Test., 2022

Innovative Practices Track: Innovative Analog Circuit Testing Technologies.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST.

[BibT_eX]

[DOI]

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

High Precision Measurement of Sub-Nano Ampere Current in ATE Environment.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Innovative Test Practices in Asia.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Accurate Testing of Precision Voltage Reference by DC-AC Conversion.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Innovative Test Practices in Japan.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Evaluation of Null Method for Operational Amplifier Short-Time Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Innovative practices on test in Japan.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017

Innovative practices session 10B innovative practices in Asia-2: From cost perspective.

[BibT_eX]

[DOI]

Kazumi Hatayama

Masahiro Ishida

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Innovative practices session 9B innovative practices in Asia-1: From quality perspective.

[BibT_eX]

[DOI]

Kazumi Hatayama

Masahiro Ishida

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

2014

A Variability-Aware Adaptive Test Flow for Test Quality Improvement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Memory block based scan-BIST architecture for application-dependent FPGA testing.

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Special session 4B: Elevator talks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

DART: Dependable VLSI test architecture and its implementation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Foreword.

[BibT_eX]

[DOI]

Kazumi Hatayama

Tsuyoshi Shinogi

IEICE Trans. Inf. Syst., 2010

Path clustering for adaptive test.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Scan based process parameter estimation through path-delay inequalities.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Small Delay Fault Model for Intra-Gate Resistive Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Estimation of Delay Test Quality and Its Application to Test Generation.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

2006

Session Abstract.

[BibT_eX]

[DOI]

Kazumi Hatayama

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2004

Opportunities with the open architecture test system.

[BibT_eX]

[DOI]

Kazumi Hatayama

Rochit Rajsuman

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

DFT Timing Design Methodology for Logic BIST.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

DFT timing design methodology for at-speed BIST.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Application of High-Quality Built-In Test to Industrial Designs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

At-Speed Built-in Test for Logic Circuits with Multiple Clocks.

[BibT_eX]

[DOI]

Kazumi Hatayama

Michinobu Nakao

Yasuo Sato

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Test Generation for Multiple-Threshold Gate-Delay Fault Model.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999

Low overhead test point insertion for scan-based BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997

A practical approach to instruction-based test generation for functional modules of VLSI processors.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Accelerated Test Points Selection Method for Scan-Based BIST.

[BibT_eX]

[DOI]

Michinobu Nakao

Kazumi Hatayama

Isao Higashi

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Application of a Design for Delay Testability Approach to High Speed Logic LSIs.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

A parallel sequential test generation system DESCARTES based on real-valued logic simulation.

[BibT_eX]

[DOI]

Hiroshi Date

Michinobu Nakao

Kazumi Hatayama

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1993

Sequential circuit test generation by real number simulation.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 1993

1992

Sequential Test Generation Based on Real-Value Logic.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1989

Enhanced Delay Test Generator for High-Speed Logic LSIs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

Kazumi Hatayama

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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