Mitsuro Saji

According to our database, Mitsuro Saji authored at least 3 papers between 2010 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

An Easily Testable Routing Architecture and Prototype Chip.

Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

2011

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Electron., 2011

2010

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010