Kazuki Inoue

According to our database, Kazuki Inoue authored at least 15 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Understanding Fake Faces.

Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka

Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018

2017

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core.

Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2017

2013

FPGA Design Framework Combined with Commercial VLSI CAD.

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2013

Defect-robust FPGA architectures for intellectual property cores in system LSI.

Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

An Easily Testable Routing Architecture and Prototype Chip.

Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

Evaluation of fault tolerant technique based on homogeneous FPGA architecture.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel physical defects recovery technique for FPGA-IP cores.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Fault detection and avoidance of FPGA in various granularities.

Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Electron., 2011

An easily testable routing architecture of FPGA.

Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition.

Masahiro Toba, Yuji Hayashi, Koji Murai, Kazuki Inoue

Proceedings of the 6th International Conference on System of Systems Engineering, 2011

An Easily Testable Routing Architecture and Efficient Test Technique.

Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core.

Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

ACM Trans. Reconfigurable Technol. Syst., 2010

2009

A Novel Local Interconnect Architecture for Variable Grain Logic Cell.

Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the Reconfigurable Computing: Architectures, 2009