Toshinori Sueyoshi

According to our database1, Toshinori Sueyoshi authored at least 93 papers between 1985 and 2018.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform.
IEICE Trans. Inf. Syst., 2018

Three Dimensional FPGA Architecture with Fewer TSVs.
IEICE Trans. Inf. Syst., 2018

Basic Knowledge to Understand FPGAs.
Proceedings of the Principles and Structures of FPGAs., 2018

2017
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.
IPSJ Trans. Syst. LSI Des. Methodol., 2017

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core.
IEICE Trans. Inf. Syst., 2017

High-level Synthesis based on Parallel Design Patterns using a Functional Language.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA based ASIC Emulator with High Speed Optical Serial Links.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds.
Proceedings of the International Conference on Field Programmable Technology, 2017

A Study of FPGA Virtualization and Accelerator Scheduling.
Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

2016
A Study of Heterogeneous Computing Design Method based on Virtualization Technology.
SIGARCH Comput. Archit. News, 2016

SLM: A Scalable Logic Module Architecture with Less Configuration Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A novel soft error tolerant FPGA architecture.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

An area compact soft error resident circuit for FPGA.
Proceedings of the International Conference on IC Design and Technology, 2016

hCODE: An open-source platform for FPGA accelerators.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015
A 3D FPGA Architecture to Realize Simple Die Stacking.
IPSJ Trans. Syst. LSI Des. Methodol., 2015

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC.
IEICE Trans. Inf. Syst., 2015

Architecture exploration of 3D FPGA to minimize internal layer connection.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Simple wafer stacking 3D-FPGA architecture.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
Blokus Duo engine on a Zynq.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Zyndroid: An Android platform for software/hardware coprocessing.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A novel three-dimensional FPGA architecture with high-speed serial communication links.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
A reconfigurable Java accelerator with software compatibility for embedded systems.
SIGARCH Comput. Archit. News, 2013

FPGA Design Framework Combined with Commercial VLSI CAD.
IEICE Trans. Inf. Syst., 2013

Three-dimensional stacking FPGA architecture using face-to-face integration.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

An FPGA design and implementation framework combined with commercial VLSI CADs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

An automatic FPGA design and implementation framework.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Defect-robust FPGA architectures for intellectual property cores in system LSI.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
An Easily Testable Routing Architecture and Prototype Chip.
IEICE Trans. Inf. Syst., 2012

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization.
IEICE Trans. Inf. Syst., 2012

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Evaluation of fault tolerant technique based on homogeneous FPGA architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel physical defects recovery technique for FPGA-IP cores.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Fault detection and avoidance of FPGA in various granularities.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

The Evaluation of an Anomaly Detection System Based on Chi-square Method.
Proceedings of the 26th International Conference on Advanced Information Networking and Applications Workshops, 2012

2011
Parallelization of the channel width search for FPGA routing.
SIGARCH Comput. Archit. News, 2011

Improving the Soft-error Tolerability of a Soft-core Processor on.
J. Next Gener. Inf. Technol., 2011

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.
IEICE Trans. Electron., 2011

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems.
IEEE Embed. Syst. Lett., 2011

An easily testable routing architecture of FPGA.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Comparison of Properties between Entropy and Chi-Square Based Anomaly Detection Method.
Proceedings of the 14th International Conference on Network-Based Information Systems, 2011

An Easily Testable Routing Architecture and Efficient Test Technique.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An Anomaly Detection System Based on Chi-Square Method with Dynamic BIN Algorithm.
Proceedings of the 2011 International Conference on Broadband, 2011

Anomaly Detection Using Chi-square Values Based on the Typical Features and the Time Deviation.
Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications, 2011

A novel reconfigurable logic device base on 3D stack technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core.
ACM Trans. Reconfigurable Technol. Syst., 2010

Power-aware FPGA routing fabrics and design tools.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A robust reconfigurable logic device based on less configuration memory logic cell.
Proceedings of the International Conference on Field-Programmable Technology, 2010

COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Early DoS/DDoS Detection Method using Short-term Statistics.
Proceedings of the CISIS 2010, 2010

DDoS Detection Technique Using Statistical Analysis to Generate Quick Response Time.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010

2009
Improvement of Execution Efficiency on the MX Core.
Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

DoS/DDoS Detection Scheme Using Statistical Method Based on the Destination Port Number.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

A novel states recovery technique for the TMR softcore processor.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A Novel Local Interconnect Architecture for Variable Grain Logic Cell.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Memory Sharing Approach for TMR Softcore Processor.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture.
Int. J. Reconfigurable Comput., 2008

Queueing Property for Different Type of Self-Similar Traffics.
Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008

Performance Framework for P2P Overlay Network.
Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008

Extraction of Characteristics of Anomaly Accessed IP Packets by the Entropy-Based Analysis.
Proceedings of the Second International Conference on Complex, 2008

Analysis of Queueing Property for Self-Similar Traffic.
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008

2007
Special Section on Reconfigurable Systems.
IEICE Trans. Inf. Syst., 2007

A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices.
IEICE Trans. Inf. Syst., 2007

Queueing Analysis for Self-similar Traffic by Simulator.
Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007

An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.
Proceedings of the FPL 2007, 2007

A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Performance Estimation of TCP under SYN Flood Attacks.
Proceedings of the First International Conference on Complex, 2007

Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.
Proceedings of the Reconfigurable Computing: Architectures, 2007

Self-Similar Property for TCP Traffic under the Bottleneck Restrainment.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Effective clustering technique to optimize routability of outer cluster nets.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
Applying the Small-World Network to Routing Structure of FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Foreword.
IEICE Trans. Inf. Syst., 2004

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2002
KITE microprocessor and CAE for computer science.
Syst. Comput. Jpn., 2002

Configurable and Reconfigurable Computing for Digital Signal Processing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distributed Syst., 2001

1996
Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers.
Syst. Comput. Jpn., 1996

1994
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
Proceedings of the International Symposium on Parallel Architectures, 1994

1993
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

1989
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.
Proceedings of the 3rd international conference on Supercomputing, 1989

1988
An overview of the Kyushu University reconfigurable parallel processor.
SIGARCH Comput. Archit. News, 1988

1986
Performance evaluation of the binary tree access mechanism in mimd type parallel computers.
Syst. Comput. Jpn., 1986

1985
Hierarchical routing bus.
Syst. Comput. Jpn., 1985


  Loading...