Mohammed Benaissa

Orcid: 0000-0001-7524-9116

According to our database1, Mohammed Benaissa authored at least 84 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Causality analysis in type 1 diabetes mellitus with application to blood glucose level prediction.
Comput. Biol. Medicine, February, 2023

2022
Blood Glucose Level Prediction: Advanced Deep-Ensemble Learning Approach.
IEEE J. Biomed. Health Informatics, 2022

Interpretable Machine Learning for Inpatient COVID-19 Mortality Risk Assessments: Diabetes Mellitus Exclusive Interplay.
Sensors, 2022

COVID-19 mortality risk assessments for individuals with and without diabetes mellitus: Machine learning models integrated with interpretation framework.
Comput. Biol. Medicine, 2022

2020
A Deep Neural Network Application for Improved Prediction of $\text{HbA}_{\text{1c}}$ in Type 1 Diabetes.
IEEE J. Biomed. Health Informatics, 2020

Intelligent Data-Driven Model for Diabetes Diurnal Patterns Analysis.
IEEE J. Biomed. Health Informatics, 2020

Hilbert Huang Transformation with filtering as a pre-treatment method for the quantitative study of glucose in near infrared spectra.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Data Fusion of Activity and CGM for Predicting Blood Glucose Levels.
Proceedings of the 5th International Workshop on Knowledge Discovery in Healthcare Data co-located with 24th European Conference on Artificial Intelligence, 2020

Multi-lag Stacking for Blood Glucose Level Prediction.
Proceedings of the 5th International Workshop on Knowledge Discovery in Healthcare Data co-located with 24th European Conference on Artificial Intelligence, 2020

2019
Simultaneous Wireless Information and Power Transfer Based on Generalized Triangular Decomposition.
IEEE Trans. Green Commun. Netw., 2019

2018
Robust Eye Blink Detection Based on Eye Landmarks and Savitzky-Golay Filtering.
Inf., 2018

Transceiver Design for Data Rate Maximization of MIMO SWIPT System Based on Generalized Triangular Decomposition.
Proceedings of the 10th International Conference on Wireless Communications and Signal Processing, 2018

Depression Detection From Eye Blink Features.
Proceedings of the 2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2018

Improved Support Vector Regression Coupled with Fourier Self-Deconvolution in the Quantitative Analysis of Glucose in NIR Spectra.
Proceedings of the 9th International Conference on Information, 2018

Accelerating Integer Based Fully Homomorphic Encryption Using Frequency Domain Multiplication.
Proceedings of the Information and Communications Security - 20th International Conference, 2018

Wireless Information and Power Transfer Based on Generalized Triangular Decomposition.
Proceedings of the IEEE Global Communications Conference, 2018

2017
High-Speed and Low-Latency ECC Processor Implementation Over GF(2<sup>m</sup>) on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Eye Blink Detection Using Facial Features Tracker.
Proceedings of the International Conference on Bioinformatics Research and Applications 2017, 2017

Detecting and Predicting Alzheimer's Disease Severity in Longitudinal Acoustic Data.
Proceedings of the International Conference on Bioinformatics Research and Applications 2017, 2017

Coupling Scatter Correction with bandpass filtering for preprocessing in the quantitative analysis of glucose from near infrared spectra.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
Parallel Implementation of ECC Point Multiplication on a Homogeneous Multi-Core Microcontroller.
Proceedings of the 12th International Conference on Mobile Ad-Hoc and Sensor Networks, 2016

Savitzky-golay coupled with digital bandpass filtering as a pre-processing technique in the quantitative analysis of glucose from near infrared spectra.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Parallel comba multiplication in GF(2163) using homogenous multicore microcontroller.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

High speed ECC implementation on FPGA over GF(2<sup>m</sup>).
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Improving the prediction performance of PLSR using RReliefF and FSD for the quantitative analysis of glucose in Near Infrared spectra.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2013
A holistic approach examining RFID design for security and privacy.
J. Supercomput., 2013

Error detecting AES using polynomial residue number systems.
Microprocess. Microsystems, 2013

Low area ECC implementation on FPGA.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Low Cost Universal Remote Patient Monitoring System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Low area memory-free FPGA implementation of the AES algorithm.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Determination of glucose concentration from near-infrared spectra using locally weighted partial least square regression.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Tele-healthcare for diabetes management: A low cost automatic approach.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
A Novel Architecture of Implementing Error Detecting AES Using PRNS.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
692-nW Advanced Encryption Standard (AES) on a 0.13-mum CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Algorithms and pipeline architectures for 2-D FFT and FFT-like transforms.
Digit. Signal Process., 2010

Efficient Time-Area Scalable ECC Processor Using <i>µ</i>-Coding Technique.
Proceedings of the Arithmetic of Finite Fields, Third International Workshop, 2010

A scalable hardware/software co-design for elliptic curve cryptography on PicoBlaze microcontroller.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Small Footprint Implementations of Scalable ECC Point Multiplication on FPGA.
Proceedings of IEEE International Conference on Communications, 2010

A scalable block cipher design using filter banks over finite fields.
Proceedings of the IEEE International Conference on Acoustics, 2010

Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Embedded Software Design of Scalable Low-Area Elliptic-Curve Cryptography.
IEEE Embed. Syst. Lett., 2009

Low Area-Scalable Hardware/Software Co-Design for Elliptic Curve Cryptography.
Proceedings of the NTMS 2009, 2009

A Low-Frequency RFID to Challenge Security and Privacy Concerns.
Proceedings of the IEEE 6th International Conference on Mobile Adhoc and Sensor Systems, 2009

A Scalable Block Cipher Design Using Filter Banks and Lifting over Finite Fields.
Proceedings of IEEE International Conference on Communications, 2009

Polynomial Residue Number System GF(2<sup>m</sup>) multiplier using trinomials.
Proceedings of the 17th European Signal Processing Conference, 2009

2008
ASIC Hardware Performance.
Proceedings of the New Stream Cipher Designs - The eSTREAM Finalists, 2008

Fast Elliptic Curve Cryptography on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Concurrent error detection in GF(2<sup>m</sup>) multiplication and its application in elliptic curve cryptography.
IET Circuits Devices Syst., 2008

Low Area Scalable Montgomery Inversion Over GF(2m).
Proceedings of the SECRYPT 2008, 2008

Price to Provide RFID Security and Privacy?.
Proceedings of the SECRYPT 2008, 2008

An improved Montgomery inversion algorithm over GF(2<sup>m</sup>) targeted for low area scalable inverter on FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

GF(2<sup>m</sup>) multiplier using Polynomial Residue Number System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero.
IEEE Trans. Computers, 2007

Fast Modulo 2<sup>n</sup> - (2<sup>n-2</sup>+1) Addition: A New Class of Adder for RNS.
IEEE Trans. Computers, 2007

Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment).
IET Inf. Secur., 2007

2006
Design of flexible GF(2<sup>m</sup>) elliptic curve cryptography processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Very small FPGA application-specific instruction processor for AES.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Limiting Flexibility in Multiplication over GF(2m): A Design Methodology.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

High-Speed Pipelined EGG Processor on FPGA.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

AES as stream cipher on a small FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
AES on FPGA from the Fastest to the Smallest.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
Iterative decoding with a hamming threshold for block turbo codes.
IEEE Commun. Lett., 2004

Adaptive combined Chase-GMD algorithms for block codes.
IEEE Commun. Lett., 2004

2003
A Novel High-Speed Configurable Viterbi Decoder for Broadband Access.
EURASIP J. Adv. Signal Process., 2003

A novel ACS scheme for area-efficient Viterbi decoders.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design space exploration of a hardware-software co-designed GF(2<sup>m</sup>) galois field processor for forward error correction and cryptography.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2000
On the implementation of soft-decision decoding for RS codes.
Proceedings of the 11th IEEE International Symposium on Personal, 2000

The implementation of generalized minimum distance decoding for Reed Solomon codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
On-Line Error Detection for Bit-Serial Multipliers in GF(2m).
J. Electron. Test., 1998

Circuit architectures for semi-bit-serial & programmable arithmetic in finite fields.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Modular Arithmetic Using Low Order Redundant Bases.
IEEE Trans. Computers, 1997

1996
Finite field inversion over the dual basis.
IEEE Trans. Very Large Scale Integr. Syst., 1996

GF(2^m) Multiplication and Division Over the Dual Basis.
IEEE Trans. Computers, 1996

Programmable bit-serial Reed-Solomon encoders.
Proceedings of the 8th European Signal Processing Conference, 1996

1995
A dual basis bit-serial systolic multiplier for GF(2<sup>m</sup>).
Integr., 1995

Bit-Serial Dual Basis Systolic Multipliers for GF 2<sup>m</sup>.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Fault-Tolerant Linear Convolution using Residue Number Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Dual Basis Systolic Divider for GF(2<sup>m</sup>).
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Bit-serial, VLSI architecture for the implementation of maximum-length number-theoretic transforms using mixed basis representation.
Proceedings of the IEEE International Conference on Acoustics, 1993


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