Michael Gössel

Affiliations:
  • University of Potsdam, Germany


According to our database1, Michael Gössel authored at least 118 papers between 1969 and 2023.

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Bibliography

2023
Modified Cross Parity Codes for Adjacent Double Error Correction.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2022
A New Decoding Method for Double Error Correcting Cross Parity Codes.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2019
A New DEC/TED Code for Fast Correction of 2-Bit-Errors.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Regular LPDC Codes with Guaranteed Minimal Hamming Distance.
J. Autom. Lang. Comb., 2018

2017
A new 3-bit burst-error correcting code.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2015
Möglichkeiten der Modellierung von Fehlern in MLC-Flash-Speichern durch Fehlergraphen.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

2014
Fault tolerant linear state machines.
Proceedings of the 15th Latin American Test Workshop, 2014

Improved circuitry for soft error correction in combinational logic in pipelined designs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computations.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A new method for correcting time and soft errors in combinational circuits.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Masking of X-Values by Use of a Hierarchically Configurable Register.
J. Electron. Test., 2011

Selective fault tolerance for finite state machines.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Implementation of Selective Fault Tolerance with conventional synthesis tools.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Reducing the area overhead of TMR-systems by protecting specific signals.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

High Performance Compaction for Test Responses with Many Unknowns.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
X-tolerant Test Data Compaction with Accelerated Shift Registers.
J. Electron. Test., 2009

Concurrent checking with split-parity codes.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment.
Proceedings of the 14th IEEE European Test Symposium, 2009

2008
A Non-linear Split Error Detection Code.
Fundam. Informaticae, 2008

New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Accelerated Shift Registers for X-tolerant Test Data Compaction.
Proceedings of the 13th European Test Symposium, 2008

2007
On-chip evaluation, compensation and storage of scan diagnosis data.
IET Comput. Digit. Tech., 2007

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Modulo <i>p</i>=3 Checking for a Carry Select Adder.
J. Electron. Test., 2006

A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.
Proceedings of the 11th European Test Symposium, 2006

Test set enrichment using a probabilistic fault model and the theory of output deviations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
J. Electron. Test., 2004

Low Cost Concurrent Error Detection for the Advanced Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder.
Proceedings of the 9th European Test Symposium, 2004

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.
Proceedings of the 2004 Design, 2004

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code.
Proceedings of the 2004 Design, 2004

Self-checking Carry-selectAdder with Sum-bit Duplication.
Proceedings of the ARCS 2004, 2004

Complementary Circuits for On-Line Detection for 1-out-of-3 Codes.
Proceedings of the ARCS 2004, 2004

2003
Multimode scan: Test per clock BIST for IP cores.
ACM Trans. Design Autom. Electr. Syst., 2003

Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output.
IEEE Trans. Computers, 2003

Parity-Based Concurrent Error Detection in Symmetric Block Ciphers.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Modulo p Checked Self-Checking Carry Select Adder.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002
Synthesis of single-output space compactors for scan-based sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Scan-Path with Directly Duplicated and Inverted Duplicated Registers.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A New Self-Checking Code-Disjoint Carry-Skip Adder.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Partially Duplicated Code-Disjoint Carry-Skip Adder.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.
Proceedings of the 2002 Design, 2002

Robust Space Compaction of Test Responses.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Design of Parameterizable Error-Propagating Space Compactors for Response Observation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Synthesis of single-output space compactors with application to scan-based IP cores.
Proceedings of ASP-DAC 2001, 2001

2000
New Self-dual Circuits for Error Detection and Testing.
VLSI Design, 2000

Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

New Self-Checking Circuits by Use of Berger-Codes.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A New Method for Concurrent Checking by Use of a 1-out-of-4 Code.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A New Method of Redundancy Addition for Circuit Optimization.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.
J. Electron. Test., 1999

Experimental Results for Self-Dual Multi-Output Combinational Circuits.
J. Electron. Test., 1999

A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits.
Proceedings of the Automata Implementation, 1999

A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Structural Approach for Space Compaction for Sequential Circuits.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Self-Checking Combinational Circuits with Unidirectionally Independent Outputs.
VLSI Design, 1998

A New Design Method for Self-Checking Unidirectional Combinational Circuits.
J. Electron. Test., 1998

On-Line Error Detection for Bit-Serial Multipliers in GF(2m).
J. Electron. Test., 1998

A Structural Approach for Space Compaction for Concurrent Checking and BIST.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Built-In Self-Test with an Alternating Output.
Proceedings of the 1998 Design, 1998

Self-Dual Duplication for Error Detection.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
A linear code-preserving signature analyzer COPMISR.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On-line error detection for finite field multipliers.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Code-Disjoint Circuits for Parity Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Self-Checking Comparator with One Periodic Output.
IEEE Trans. Computers, 1996

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST.
J. Electron. Test., 1996

Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Self-dual parity checking-A new method for on-line testing.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
BIST with negligible aliasing through random cover circuits.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Detection of Permanent Hardware Faults of a Floating Point Adder by Pseudoduplication.
Proceedings of the Dependable Computing, 1994

Design of Cover Circuits for Monitoring the Output of a MISA.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs.
J. Electron. Test., 1993

Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design.
Proceedings of the VLSI 93, 1993

Monitoring BIST by covers.
Proceedings of the European Design Automation Conference 1993, 1993

Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
Self-testing and self-checking combinational circuits with weakly independent outputs.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
Pseudoduplication of floating-point addition. A method of compiler generated checking of permanent hardware faults.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Optimal Error Detection Circuits for Sequential Circuits with Observable States.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

1989
Parallel matrix multiplication on an array-logical processor.
Proceedings of the Recent Issues in Pattern Analysis and Recognition, 1989

Linear image operations on the A6472 image processing system by use of the residue arithmetics.
Proceedings of the Recent Issues in Pattern Analysis and Recognition, 1989

Parallel computing of line-codings by use of a display processor system and the parallel determination of a discrete curvature.
Proceedings of the Recent Issues in Pattern Analysis and Recognition, 1989

Parallel Access, to rectangles.
Proceedings of the Recent Issues in Pattern Analysis and Recognition, 1989

1988
Bitgenaue schnelle Arithmethik mit dem Bildverarbeitunssystem BVS A 6472.
Angew. Inform., 1988

Parallel memories for straight line and rectangle access.
Proceedings of the Parcella '88, 1988

1987
Memories for Parallel Subtree-Access.
Proceedings of the Parallel Algorithms and Architectures, 1987

1985
Sets of Permutations and Their Realization by Permutation Networks.
J. Inf. Process. Cybern., 1985

1983
Bemerkung über die Existenz von Signaturregistern zur Erkennung geradzahliger Fehler.
Elektron. Rechenanlagen, 1983

1980
Invariant Relations for Automata - A Proposal.
J. Inf. Process. Cybern., 1980

1977
On the Characterization of Linear and Linearizable Automata by a Superposition Principle.
Math. Syst. Theory, 1977

Verallgemeinerte Superposition bei binären Automaten.
Acta Cybern., 1977

1975
Ein verallgemeinertes Superpositionsprinzig für binäre Automaten.
J. Inf. Process. Cybern., 1975

1973
Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten II.
J. Inf. Process. Cybern., 1973

Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten I.
J. Inf. Process. Cybern., 1973

Über stabile Umkehrautomaten linearer Automaten.
J. Inf. Process. Cybern., 1973

1972
Über Momente der Autokorrelationsfunktion eines Zeichens.
J. Inf. Process. Cybern., 1972

Zur Realisierung stochastischer Automaten aus Zufallsgeneratoren und determinierten Automaten.
J. Inf. Process. Cybern., 1972

1971
Zur minimalen Modellbildung bei linearen diskreten Systemen.
J. Inf. Process. Cybern., 1971

Über die Reduktion eines erweiterten linearen Automaten.
J. Inf. Process. Cybern., 1971

Versuch einer automatentheoretischen Beschreibung von Selektionsprozessen.
Acta Cybern., 1971

1970
Abstandsmatrix eines Zeichens.
J. Inf. Process. Cybern., 1970

1969
Ein Algorithmus für die Diagrammtechnik der Greenschen Funktion.
J. Inf. Process. Cybern., 1969


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