Mohammed Sayed

Orcid: 0000-0002-1944-9436

According to our database1, Mohammed Sayed authored at least 24 papers between 2002 and 2022.

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Bibliography

2022
Developing Novel Criteria to Classify ARDS Severity using a Machine Learning Approach
PhD thesis, 2022

2019
Modelling ICU Patients to Improve Care Requirements and Outcome Prediction of Acute Respiratory Distress Syndrome: A Supervised Learning Approach.
Proceedings of the Artificial Intelligence in Medicine: Knowledge Representation and Transparent and Explainable Systems, 2019

2018
Sequence homology in circular RNA detection.
Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018

Neural Networks Based Fractional Pixel Motion Estimation for HEVC.
Proceedings of the 2018 IEEE International Symposium on Multimedia, 2018

2016
Proceedings of the 15th Annual UT-KBRIN Bioinformatics Summit 2016: Cadiz, KY, USA. 8-10 April 2016.
BMC Bioinform., August, 2016

2012
Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation.
J. Signal Process. Syst., 2012

2010
Video-Active RAM: A processor-in-memory architecture for video coding applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Low-complexity algorithm for fractional-pixel motion estimation.
Proceedings of the International Conference on Image Processing, 2009

A fast architecture for exhaustive search block matching algorithm with MPEG-4 applications.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2006
A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices.
J. VLSI Signal Process., 2006

An affine-based algorithm and SIMD architecture for video compression with low bit-rate applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Coset enumeration of groups generated by symmetric sets of involutions.
Int. J. Math. Math. Sci., 2005

Double-coset enumeration algorithm for symmetrically generated groups.
Int. J. Math. Math. Sci., 2005

A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
A Computational-ram (c-ram) Architecture for Real-time Mesh-based Video Motion Tracking Part 2: Motion Compensation.
J. Circuits Syst. Comput., 2004

A Computational-ram (c-ram) Architecture for Real-time Mesh-based Video Motion Tracking Part 1: Motion Estimation.
J. Circuits Syst. Comput., 2004

A novel embedded memory architecture for real-time mesh-based motion estimation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Partial Discharge Classification Through Wavelet Packets of Their Modulated Ultrasonic Emission.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2004

A novel motion estimation method for mesh-based video motion tracking.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A half-pel motion estimation architecture for MPEG-4 applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologies.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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