Monalisa Das

According to our database, Monalisa Das authored at least 8 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2026

Division-Free Four-Way Toom-Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs.

Monalisa Das, Babita Jajodia

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

2025

Hybrid Recursive Karatsuba Multiplications on FPGAs.

Monalisa Das, Babita Jajodia

IEEE Embed. Syst. Lett., August, 2025

ATP-Optimized Implementation of Four-Way Toom-Cook Multiplications on FPGAs for Large Integer Arithmetic.

Monalisa Das, Babita Jajodia

Circuits Syst. Signal Process., May, 2025

Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs.

Monalisa Das, Babita Jajodia

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

2022

FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives.

Monalisa Das, Babita Jajodia

Proceedings of the 19th International SoC Design Conference, 2022

Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA.

Monalisa Das, Babita Jajodia

Proceedings of the 19th International SoC Design Conference, 2022

2019

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.

Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2017

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.

Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017