Bidyut K. Bhattacharyya
Orcid: 0000-0003-3933-3008
According to our database1,
Bidyut K. Bhattacharyya
authored at least 27 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2022
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.
Integr., 2022
A cost-effective and load-balanced controller placement method in software-defined networks.
Int. J. Netw. Manag., 2022
A comprehensive study of different objectives and solutions of controller placement problem in software-defined networks.
Trans. Emerg. Telecommun. Technol., 2022
2021
Wirel. Pers. Commun., 2021
Centroid-Based Routing protocol with moving sink node for uniform and non-uniform distribution of wireless sensor nodes.
J. Supercomput., 2021
A PVT aware differential delay circuit and its performance variation due to power supply noise.
Integr., 2021
A new optimization technique to solve the latency aware controller placement problem in software defined networks.
Trans. Emerg. Telecommun. Technol., 2021
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time.
Circuits Syst. Signal Process., 2021
Fuzzy logic-based VANET routing method to increase the QoS by considering the dynamic nature of vehicles.
Computing, 2021
Buck Topology Powered Exclusively by Supercapacitor Modules - A Battery-Less Design Concept.
IEEE Access, 2021
2020
Microelectron. J., 2020
Segmentation of images through curve fitting analysis by modified Vandermonde matrix and modified Gram-Schmidt method.
IET Image Process., 2020
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020
2019
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.
J. Circuits Syst. Comput., 2018
IET Image Process., 2018
IEEE Consumer Electron. Mag., 2018
2017
A 65 nm Design of 0.6 V/8.98 <i>μ</i>W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications.
J. Low Power Electron., 2017
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit.
Integr., 2017
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect.
Integr., 2017
Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect.
Turkish J. Electr. Eng. Comput. Sci., 2017
Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users.
IEEE Consumer Electron. Mag., 2017
Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment.
IEEE Consumer Electron. Mag., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017