Morgan Deters

Orcid: 0000-0001-6218-8107

According to our database1, Morgan Deters authored at least 28 papers between 2001 and 2019.

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Bibliography

2019
Refutation-based synthesis in SMT.
Formal Methods Syst. Des., 2019

2016
Expressive Completeness of Separation Logic with Two Variables and No Separating Conjunction.
ACM Trans. Comput. Log., 2016

Temporal logics on strings with prefix relation.
J. Log. Comput., 2016

An efficient SMT solver for string constraints.
Formal Methods Syst. Des., 2016

Efficient solving of string constraints for security analysis.
Proceedings of the Symposium and Bootcamp on the Science of Security, 2016

2015
Two-Variable Separation Logic and Its Inner Circle.
ACM Trans. Comput. Log., 2015

Separation logics and modalities: a survey.
J. Appl. Non Class. Logics, 2015

On Counterexample Guided Quantifier Instantiation for Synthesis in CVC4.
CoRR, 2015

Fine Grained SMT Proofs for the Theory of Fixed-Width Bit-Vectors.
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2015

Counterexample-Guided Quantifier Instantiation for Synthesis in SMT.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
A tour of CVC4: How it works, and how to use it.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

A DPLL(T) Theory Solver for a Theory of Strings and Regular Expressions.
Proceedings of the Computer Aided Verification - 26th International Conference, 2014

The Effects of Modalities in Separation Logics (Extended Abstract).
Proceedings of the Advances in Modal Logic 10, 2014

2013
6 Years of SMT-COMP.
J. Autom. Reason., 2013

Witness Runs for Counter Machines - (Abstract).
Proceedings of the Automated Reasoning with Analytic Tableaux and Related Methods, 2013

Witness Runs for Counter Machines.
Proceedings of the Frontiers of Combining Systems, 2013

Quantifier Instantiation Techniques for Finite Model Finding in SMT.
Proceedings of the Automated Deduction - CADE-24, 2013

2012
The 2012 SMT Competition.
Proceedings of the 10th International Workshop on Satisfiability Modulo Theories, 2012

2011
Reducing Chaos in SAT-Like Search: Finding Solutions Close to a Given One.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2011, 2011

Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2010
The SMT Execution Service: Features, Fairness, and the Future.
Proceedings of the Workshop on Evaluation Methods for Solvers, 2010

2009
Verified programming in Guru.
Proceedings of the 3rd ACM Workshop Programming Languages meets Program Verification, 2009

2008
Design and Results of the 3rd Annual Satisfiability Modulo Theories Competition (SMT-Comp 2007).
Int. J. Artif. Intell. Tools, 2008

2007
Signature Compilation for the Edinburgh Logical Framework.
Proceedings of the Second International Workshop on Logical Frameworks and Meta-Languages: Theory and Practice, 2007

2005
Static determination of allocation rates to support real-time garbage collection.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

2004
Automated Reference-Counted Object Recycling for Real-Time Jav.
Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

2002
Automated discovery of scoped memory regions for real-time Java.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002

2001
Storage Allocation for Real-Time, Embedded Systems.
Proceedings of the Embedded Software, First International Workshop, 2001


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