Mostafa Darvishi

According to our database, Mostafa Darvishi authored at least 9 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation.

Mostafa Darvishi

CoRR, March, 2026

Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs.

Mostafa Darvishi

CoRR, January, 2026

2025

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor.

Mostafa Darvishi

CoRR, December, 2025

A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs.

Mostafa Darvishi

CoRR, December, 2025

Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies.

Mostafa Darvishi

CoRR, October, 2025

2024

Application of FPGA in Power Electronics: State-of-the-Art, Challenges, and Future.

Mostafa Darvishi, Hani Vahedi

Proceedings of the 50th Annual Conference of the IEEE Industrial Electronics Society, 2024

2020

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics.

Mostafa Darvishi

CoRR, 2020

2018

Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA.

Mostafa Darvishi, Yves Audet, Yves Blaquière

CoRR, 2018

2015

Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation.

Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault

CoRR, 2015