Claude Thibeault
Orcid: 0000-0003-1765-9170
According to our database1,
Claude Thibeault
authored at least 94 papers
between 1990 and 2023.
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Bibliography
2023
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
2021
IET Comput. Digit. Tech., 2021
2020
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics.
J. Electron. Test., 2019
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
2018
J. Signal Process. Syst., 2018
On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
2017
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
A new delay testing signal scheme robust to power distribution network impedance variation.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
2016
IEEE Trans. Commun., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays.
IEEE Trans. Aerosp. Electron. Syst., 2016
Microelectron. Reliab., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Efficient identification of Faces in video Streams using low-Power Multi-Core Devices.
Proceedings of the Handbook of Pattern Recognition and Computer Vision, 5th Ed., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation.
CoRR, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations.
CoRR, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014
Multi-abstraction level signature generation and comparison based on radiation single event upset.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
2013
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.
J. Electron. Test., 2013
Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG.
CoRR, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013
Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2013
2012
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors.
J. Electron. Test., 2012
Proceedings of the 31st IEEE Military Communications Conference, 2012
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
2011
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Leveraging green communications for carbon emission reductions: Techniques, testbeds, and emerging carbon footprint standards.
IEEE Commun. Mag., 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2009
2007
Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors.
IET Comput. Digit. Tech., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
J. Electron. Test., 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
2000
IEEE Trans. Computers, 2000
J. Electron. Test., 2000
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1999
A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations.
IEEE Trans. Computers, 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
1997
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
Panel Summaries.
IEEE Des. Test Comput., 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
1994
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers, 1994
Using Fourier Analysis to Enhance IC Testability.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Some Results on Yield and Local Design Rule Relaxation.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits.
J. Circuits Syst. Comput., 1992
J. Electron. Test., 1992
1990
Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990