Yves Blaquière

Orcid: 0000-0001-6204-7427

According to our database1, Yves Blaquière authored at least 58 papers between 1990 and 2024.

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Bibliography

2024
Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Toward a Polysilicon-Based Electrostatically Actuated DC MEMS Switch.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Toward 2.5D Structures for Multi-Channel MEMS Acoustic-Based Digital Isolators using Through Silicon Openings.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

A 3.3 V 0.1-1 A Hybrid Buck-Boost Converter with 85-97 % Power Efficiency Range Highly-Suited for Battery-Powered Devices using Low-Profile High-DCR Inductor.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

A Reconfigurable Power System-in-Package Module using GaN HEMTs and IC Bare Dies on LTCC Substrate: Design - Implementation - Experiment and Future Directions.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2021
Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays.
IEEE Trans. Instrum. Meas., 2021

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Towards an LTCC SiP for Control System in Safety-Critical Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA.
IET Circuits Devices Syst., 2020

In-FPGA Instrumentation Framework for OpenCL-Based Designs.
IEEE Access, 2020

A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Toward In-System Monitoring of OpenCL-Based Designs on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A pattern-based routing algorithm for a novel electronic system prototyping platform.
Integr., 2018

Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits.
Integr., 2018

Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA.
CoRR, 2018

2017
Sub-ps resolution programmable delays implemented in a Xilinx FPGA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Towards an efficient SEU effects emulation on SRAM-based FPGAs.
Microelectron. Reliab., 2016

A novel spatially configurable differential interface for an electronic system prototyping platform.
Integr., 2016

A compact spatially configurable differential input stage for a field programmable interconnection network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation.
CoRR, 2015

Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A netlist pruning tool for an electronic system prototyping platform.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

An interface for the I<sup>2</sup>C protocol in the WaferBoard™.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Software rendering methods to display wafer scale integrated circuit dataset.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
A new approach for pin detection for an electronic system prototyping reconfigurable platform.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

SoC systems thermal monitoring using embedded sensor cells unit.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Propagating analog signals through a fully digital network on an electronic system prototyping platform.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Machine-learning framework for automatic netlist creation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A spatially reconfigurable fast differential interface for a wafer scale configurable platform.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Workflow for an Electronic Configurable Prototyping System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Digital signal propagation on a wafer-scale smart active programmable interconnect.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2000
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1996
Timing analysis speed-up using a hierarchical and a multimode approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Cost analysis of a new algorithmic-based soft-error tolerant architecture.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1990
VHDL design of a priority interrupt controller and synchronizer for the MC68008.
Microprocess. Microsystems, 1990


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