Moucheng Yang

According to our database, Moucheng Yang authored at least 6 papers between 2015 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

RLUT: A Reduced LUT Architecture with Fine-Grained Scalability and Its Automatic Design Flow for Large Frequent Functions.

Moucheng Yang, Chengyu Zeng, Kaixiang Zhu, Lingli Wang

ACM Trans. Reconfigurable Technol. Syst., September, 2025

2023

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions.

Moucheng Yang, Kaixiang Zhu, Lingli Wang, Xuegong Zhou

Proceedings of the International Conference on Field Programmable Technology, 2023

2021

Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning.

Xiaoxi Wang, Moucheng Yang, Zhen Li, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2021

2019

A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass Spectrometry.

Moucheng Yang, Tao Chen, Xuegong Zhou, Liang Zhao, Yunping Zhu, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2019

2017

A scalable hybrid architecture for high performance data-parallel applications.

Moucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou, Shaojun Wang, Lingli Wang

Proceedings of the International Conference on Field Programmable Technology, 2017

2015

An automated test framework for SRAM-based FPGA.

Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015