Kaixiang Zhu

Orcid: 0009-0007-9096-3722

According to our database1, Kaixiang Zhu authored at least 13 papers between 2021 and 2026.

Collaborative distances:

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits.
ACM Trans. Design Autom. Electr. Syst., March, 2026

An End-to-End Compilation Flow with Reinforcement Learning-Guided Logic Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Collaborative Framework for Multi-Level Multi-Objective Design Space Exploration.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

Novel Multi-Corner Delay Padding using Path Relationship Analysis and Dual Decomposition.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
RLUT: A Reduced LUT Architecture with Fine-Grained Scalability and Its Automatic Design Flow for Large Frequent Functions.
ACM Trans. Reconfigurable Technol. Syst., September, 2025

DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

GEF: A GNN-Based Evaluation Framework for FPGA Routing Architecture.
Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning.
CoRR, 2024

2023
DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions.
Proceedings of the International Conference on Field Programmable Technology, 2023

Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Automatic Optimization Method of Combinational Logic Loops in CGRA.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021
Developing an Online Examination Timetabling System Using Artificial Bee Colony Algorithm in Higher Education.
Proceedings of the Broadband Communications, Networks, and Systems, 2021


  Loading...