Kaixiang Zhu
Orcid: 0009-0007-9096-3722
According to our database1,
Kaixiang Zhu authored at least 13 papers
between 2021 and 2026.
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Bibliography
2026
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits.
ACM Trans. Design Autom. Electr. Syst., March, 2026
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
Proceedings of the Design, Automation & Test in Europe Conference, 2026
Novel Multi-Corner Delay Padding using Path Relationship Analysis and Dual Decomposition.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
2025
RLUT: A Reduced LUT Architecture with Fine-Grained Scalability and Its Automatic Design Flow for Large Frequent Functions.
ACM Trans. Reconfigurable Technol. Syst., September, 2025
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning.
CoRR, 2024
2023
Proceedings of the International Conference on Field Programmable Technology, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2021
Developing an Online Examination Timetabling System Using Artificial Bee Colony Algorithm in Higher Education.
Proceedings of the Broadband Communications, Networks, and Systems, 2021