Mun-Yang Park

According to our database, Mun-Yang Park authored at least 4 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.

Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu

IET Circuits Devices Syst., 2013

2012

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.

Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2004

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver.

Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2004

A 1.8V triode-type transconductor and its application to a 10MHz 3^rd-order Chebyshev low pass filter.

Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004