Sangjin Byun

According to our database, Sangjin Byun authored at least 18 papers between 2003 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2020

A Poly Resistor Based Time Domain CMOS Temperature Sensor with 9b SAR and Fine Delay Line.

Zhiwei Xu, Sangjin Byun

Sensors, 2020

Categorization and Characterization of Time Domain CMOS Temperature Sensors.

Sangjin Byun

Sensors, 2020

2017

On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors.

Chung Hwan Son, Sangjin Byun

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line.

Sangjin Byun

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector.

Sangjin Byun

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling.

Sangjin Byun

IET Circuits Devices Syst., 2016

1∼3 GHz VCO with rail-to-rail V_CONT range.

Sangjin Byun

IEICE Electron. Express, 2016

2014

Analysis and Design of CMOS Received Signal Strength Indicator.

Sangjin Byun

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.

Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu

IET Circuits Devices Syst., 2013

2012

Simple odd number frequency divider with 50% duty cycle.

Sangjin Byun, Chung Hwan Son, Jae Joon Kim

IEICE Electron. Express, 2012

2011

A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications.

Jae Joon Kim, Chang-Hyuk Cho, Kwan-Yeob Chae, Sangjin Byun

IEICE Electron. Express, 2011

2010

Charge Pump circuit with wide range digital leakage current mismatch compensator.

Sangjin Byun, Jae Hoon Shim

IEICE Electron. Express, 2010

2008

A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology.

Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2008

2006

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.

Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2006

A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS.

Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.

Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer.

Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim

IEEE J. Solid State Circuits, 2005

2003

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator.

Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim

IEEE J. Solid State Circuits, 2003